Patents by Inventor Teng YUAN

Teng YUAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11942906
    Abstract: The present invention provides a transmitter including a mixer, a harmonic impedance adjustment circuit and an amplifier. The mixer is configured to mix a first baseband signal with a first oscillation signal to generate a first mixed signal to a first node, and to mix a second baseband signal with a second oscillation signal to generate a second mixed signal to a second node. The harmonic impedance adjustment circuit is coupled between the first node and the second node, and is configured to reduce harmonic components of the first mixed signal and the second mixed signal to generate an adjusted first mixed signal and an adjusted second mixed signal. The amplifier is coupled to the harmonic impedance adjustment circuit, and is configured to generate an amplified signal according to the adjusted first mixed signal and the adjusted second mixed signal.
    Type: Grant
    Filed: February 7, 2022
    Date of Patent: March 26, 2024
    Assignee: Realtek Semiconductor Corp.
    Inventors: Ting-Yao Huang, Teng-Yuan Chang, Po-Chih Wang, Ka-Un Chan
  • Publication number: 20240063975
    Abstract: A dynamic adjustment method for RS reception is provided. The dynamic adjustment method for RS reception includes the following steps. A processor of an apparatus may detect at least one channel condition to generate a detection result. Then, the processor may determine an RS reception scheduling based on the detection result. Then, the processor may perform an RS reception based on the RS reception scheduling to receive RSs from a network node.
    Type: Application
    Filed: August 8, 2023
    Publication date: February 22, 2024
    Inventors: Hsien-Wen HU, Qian-Zhi HUANG, Ying-Hsuan SU, Teng-Yuan CHANG, Cheng-Yu TSAI
  • Publication number: 20240047408
    Abstract: An embodiment semiconductor device may include an electrical interconnect layer, a bonding pad electrically coupled to the electrical interconnect layer, a stacked film structure including a first film partially covering a surface of the bonding pad and a second film partially covering the first film, a first aperture formed in the first film over a portion of the surface of the bonding pad, a second aperture formed in the second film such that the second aperture is larger than the first aperture and is formed over the first aperture such that the first aperture is located entirely below an area of the second aperture, and a solder material portion formed in contact with the bonding pad. The solder material portion may include a first width that is less than a size of the second aperture such that the solder material portion does not contact the second film.
    Type: Application
    Filed: August 8, 2022
    Publication date: February 8, 2024
    Inventors: Amram Eitan, Wen-Yi Lin, Teng-Yuan Lo
  • Publication number: 20230346189
    Abstract: An obstacle avoidance mechanism applied to a sweeping robot, the sweeping robot comprises a body, a baffle and a road wheel, the baffle is arranged on an exterior side of the body, the baffle is arranged at a first distance from the body, the obstacle avoidance mechanism comprises a shield module and a photosensitive module. When the baffle collides with the an obstacle object, the light path of the photosensitive module is blocked by the shield module, so as to send out a first signal to make the road wheel stop moving forward or turn, and realize the obstacle avoidance function of the sweeping robot and enhance its service life.
    Type: Application
    Filed: April 10, 2023
    Publication date: November 2, 2023
    Inventor: Teng-Yuan CHANG
  • Publication number: 20230346178
    Abstract: An anti-collision mechanism comprises a body, a collision baffle, a magnetic element, and a magnetic field sensor, and the anti-collision mechanism is configured to be applicable to a sweeping robot. The magnetic field sensor is arranged at a distance from the magnetic element, the magnetic field sensor is configured to detect a change in the magnetic field intensity caused by a change in the distance between the magnetic field sensor and the magnetic element. When the collision occurs, the magnetic element is closer to the magnetic field sensor to make the magnetic field intensity change, thus generating signals to stop or turn the sweeping robot, which can realize the obstacle avoidance of the sweeping robot and enhance the service life. The sweeping robot is also provided.
    Type: Application
    Filed: April 7, 2023
    Publication date: November 2, 2023
    Inventors: CHIEN-YUAN HUANG, TENG-YUAN CHANG
  • Publication number: 20230253300
    Abstract: A chip package structure includes an interposer structure that contains a package-side redistribution structure, an interposer core assembly, and a die-side redistribution structure. The interposer core assembly includes at least one silicon substrate interposer, and each of the at least one silicon substrate interposer includes a respective silicon substrate, a respective set of through-silicon via (TSV) structures vertically extending through the respective silicon substrate, a respective set of interconnect-level dielectric layers embedding a respective set of metal interconnect structures, and a respective set of metal bonding structures that are electrically connected to the die-side redistribution structure. The chip package structure includes at least two semiconductor dies that are attached to the die-side redistribution structure, and an epoxy molding compound (EMC) multi-die frame that laterally encloses the at least two semiconductor dies.
    Type: Application
    Filed: March 28, 2023
    Publication date: August 10, 2023
    Inventors: Kuo Lung Pan, Yu-Chia Lai, Teng-Yuan Lo, Mao-Yen Chang, Po-Yuan Teng, Chen-Hua YU, Chung-Shi Liu, Hao-Yi Tsai, Ting-Hao Kuo
  • Patent number: 11646255
    Abstract: A chip package structure includes an interposer structure that contains a package-side redistribution structure, an interposer core assembly, and a die-side redistribution structure. The interposer core assembly includes at least one silicon substrate interposer, and each of the at least one silicon substrate interposer includes a respective silicon substrate, a respective set of through-silicon via (TSV) structures vertically extending through the respective silicon substrate, a respective set of interconnect-level dielectric layers embedding a respective set of metal interconnect structures, and a respective set of metal bonding structures that are electrically connected to the die-side redistribution structure. The chip package structure includes at least two semiconductor dies that are attached to the die-side redistribution structure, and an epoxy molding compound (EMC) multi-die frame that laterally encloses the at least two semiconductor dies.
    Type: Grant
    Filed: March 18, 2021
    Date of Patent: May 9, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Kuo Lung Pan, Yu-Chia Lai, Tin-Hao Kuo, Hao-Yi Tsai, Chung-Shi Liu, Chen-Hua Yu, Po-Yuan Teng, Teng-Yuan Lo, Mao-Yen Chang
  • Publication number: 20230120754
    Abstract: A computing device captures a live video of a user's head and generates a virtual mirror displaying the live video of the user's head. The computing device tracks ear regions on the user's head and performs virtual application of a set of earrings on the ear regions on the user's head. The computing device monitors for a target motion among a plurality of predefined target motions by the user. When at least one target motion is detected, the computing device changes the set of earrings with another set of earrings.
    Type: Application
    Filed: October 13, 2022
    Publication date: April 20, 2023
    Inventor: TENG-YUAN HSIAO
  • Patent number: 11623951
    Abstract: Isolated antibodies that bind specifically to R-spondin 3 (RSPO3) are described. Also described herein are compositions containing the antibodies and methods of using the antibodies to treat cancer and detect RSPO3.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: April 11, 2023
    Assignee: National Health Research Institutes
    Inventors: Tsu-An Hsu, Hui-Chen Hung, Teng-Yuan Chang, Chuan Shih
  • Publication number: 20230090895
    Abstract: In an embodiment, a device includes: a first redistribution structure including a first dielectric layer; a die adhered to a first side of the first redistribution structure; an encapsulant laterally encapsulating the die, the encapsulant being bonded to the first dielectric layer with first covalent bonds; a through via extending through the encapsulant; and first conductive connectors electrically connected to a second side of the first redistribution structure, a subset of the first conductive connectors overlapping an interface of the encapsulant and the die.
    Type: Application
    Filed: November 21, 2022
    Publication date: March 23, 2023
    Inventors: Kuo Lung Pan, Shu-Rong Chun, Teng-Yuan Lo, Hung-Yi Kuo, Chih-Horng Chang, Tin-Hao Kuo, Hao-Yi Tsai
  • Publication number: 20230066968
    Abstract: A semiconductor package includes a semiconductor device, an encapsulating material, a redistribution structure, and an adhesive residue. The encapsulating material encapsulates a first part of a side surface of the semiconductor device. The redistribution structure is disposed over the semiconductor device and a first side of the encapsulating material. The adhesive residue is disposed over a second side of the encapsulating material opposite to the first side and surrounding the semiconductor device, wherein the adhesive residue encapsulates a second part of the side surface of the semiconductor device.
    Type: Application
    Filed: August 30, 2021
    Publication date: March 2, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Sung Huang, Ming-Hung Tseng, Yen-Liang Lin, Ban-Li Wu, Hsiu-Jen Lin, Teng-Yuan Lo, Hao-Yi Tsai
  • Patent number: 11508656
    Abstract: In an embodiment, a device includes: a first redistribution structure including a first dielectric layer; a die adhered to a first side of the first redistribution structure; an encapsulant laterally encapsulating the die, the encapsulant being bonded to the first dielectric layer with first covalent bonds; a through via extending through the encapsulant; and first conductive connectors electrically connected to a second side of the first redistribution structure, a subset of the first conductive connectors overlapping an interface of the encapsulant and the die.
    Type: Grant
    Filed: June 28, 2021
    Date of Patent: November 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuo Lung Pan, Shu-Rong Chun, Teng-Yuan Lo, Hung-Yi Kuo, Chih-Horng Chang, Tin-Hao Kuo, Hao-Yi Tsai
  • Patent number: 11508671
    Abstract: A manufacturing method of a semiconductor package includes at least the following steps. A rear surface of a semiconductor die is attached to a patterned dielectric layer of a first redistribution structure through a die attach material, where a thickness of a portion of the die attach material filling a gap between the rear surface of the semiconductor die and a recessed area of the patterned dielectric layer is greater than a thickness of another portion of the die attach material interposed between the rear surface of the semiconductor die and a non-recessed area of the patterned dielectric layer. An insulating encapsulant is formed on the patterned dielectric layer of the first redistribution structure to cover the semiconductor die and the die attach material. Other methods for forming a semiconductor package are also provided.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: November 22, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Yuan Teng, Hao-Yi Tsai, Tin-Hao Kuo, Ching-Yao Lin, Teng-Yuan Lo, Chih Wang
  • Publication number: 20220367301
    Abstract: A package structure and a method of forming the same are provided. A method includes forming first electrical connectors and second electrical connectors on a first side of an interposer wafer. An integrated circuit die is bonded to the first side of the interposer wafer using the first electrical connectors. A stiffener structure is attached to the first side of the interposer wafer adjacent the integrated circuit die. The stiffener structure covers the second electrical connectors in a plan view. The integrated circuit die and the stiffener structure are encapsulated with a first encapsulant. The interposer wafer and the stiffener structure are singulated to form a stacked structure.
    Type: Application
    Filed: July 28, 2022
    Publication date: November 17, 2022
    Inventors: Teng-Yuan Lo, Lipu Kris Chuang, Hsin-Yu Pan
  • Publication number: 20220302003
    Abstract: A chip package structure includes an interposer structure that contains a package-side redistribution structure, an interposer core assembly, and a die-side redistribution structure. The interposer core assembly includes at least one silicon substrate interposer, and each of the at least one silicon substrate interposer includes a respective silicon substrate, a respective set of through-silicon via (TSV) structures vertically extending through the respective silicon substrate, a respective set of interconnect-level dielectric layers embedding a respective set of metal interconnect structures, and a respective set of metal bonding structures that are electrically connected to the die-side redistribution structure. The chip package structure includes at least two semiconductor dies that are attached to the die-side redistribution structure, and an epoxy molding compound (EMC) multi-die frame that laterally encloses the at least two semiconductor dies.
    Type: Application
    Filed: March 18, 2021
    Publication date: September 22, 2022
    Inventors: Kuo Lung PAN, Yu-Chia LAI, Tin-Hao KUO, Hao-Yi TSAI, Chung-Shi LIU, Chen-Hua YU, Po-Yuan TENG, Teng-Yuan LO, Mao-Yen CHANG
  • Publication number: 20220298282
    Abstract: The present invention relates to a photo-induced cationic polymerized pure vegetable oil-based polymer and a preparation method and use thereof. The preparation method comprises the following steps: mixing a dry oil, an epoxy vegetable oil and an initiator uniformly, irradiating to initiate a photo-curing reaction, and then placing at ambient temperature, and continuing to a heat-curing reaction so as to obtain a photo-induced cationic polymerized pure vegetable oil-based polymer. In the present invention, vegetable oil resources which are low in price, widespread, and easy to regenerate are used to prepare the pure vegetable oil-based polymers instead of the fossil-derived monomers completely, thereby achieving the efficient use of vegetable oils. In the present invention, an unconventional photo-induced heat frontal polymerization technology is used to prepare the pure vegetable oil-based polymer, thereby achieving a photo-thermal dual curing reaction of a vegetable oil system without heating.
    Type: Application
    Filed: August 4, 2020
    Publication date: September 22, 2022
    Applicants: SOUTH CHINA AGRICULTURAL UNIVERSITY, GUANGDONG LANYANG TECHNOLOGY CO., LTD.
    Inventors: Teng YUAN, Jinqing HUANG, Zhuohong YANG, Yaliang XIAO, Xiaoping LI
  • Patent number: 11450581
    Abstract: A package structure and a method of forming the same are provided. A method includes forming first electrical connectors and second electrical connectors on a first side of an interposer wafer. An integrated circuit die is bonded to the first side of the interposer wafer using the first electrical connectors. A stiffener structure is attached to the first side of the interposer wafer adjacent the integrated circuit die. The stiffener structure covers the second electrical connectors in a plan view. The integrated circuit die and the stiffener structure are encapsulated with a first encapsulant. The interposer wafer and the stiffener structure are singulated to form a stacked structure.
    Type: Grant
    Filed: January 29, 2021
    Date of Patent: September 20, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Teng-Yuan Lo, Lipu Kris Chuang, Hsin-Yu Pan
  • Publication number: 20220286096
    Abstract: The present invention provides a transmitter including a mixer, a harmonic impedance adjustment circuit and an amplifier. The mixer is configured to mix a first baseband signal with a first oscillation signal to generate a first mixed signal to a first node, and to mix a second baseband signal with a second oscillation signal to generate a second mixed signal to a second node. The harmonic impedance adjustment circuit is coupled between the first node and the second node, and is configured to reduce harmonic components of the first mixed signal and the second mixed signal to generate an adjusted first mixed signal and an adjusted second mixed signal. The amplifier is coupled to the harmonic impedance adjustment circuit, and is configured to generate an amplified signal according to the adjusted first mixed signal and the adjusted second mixed signal.
    Type: Application
    Filed: February 7, 2022
    Publication date: September 8, 2022
    Applicant: Realtek Semiconductor Corp.
    Inventors: Ting-Yao Huang, Teng-Yuan Chang, Po-Chih Wang, Ka-Un Chan
  • Publication number: 20220068736
    Abstract: A package structure and a method of forming the same are provided. A method includes forming first electrical connectors and second electrical connectors on a first side of an interposer wafer. An integrated circuit die is bonded to the first side of the interposer wafer using the first electrical connectors. A stiffener structure is attached to the first side of the interposer wafer adjacent the integrated circuit die. The stiffener structure covers the second electrical connectors in a plan view. The integrated circuit die and the stiffener structure are encapsulated with a first encapsulant. The interposer wafer and the stiffener structure are singulated to form a stacked structure.
    Type: Application
    Filed: January 29, 2021
    Publication date: March 3, 2022
    Inventors: Teng-Yuan Lo, Lipu Kris Chuang, Hsin-Yu Pan
  • Publication number: 20220067380
    Abstract: A media casting device detects facial feature points of a beauty advisor and detects the beauty advisor performing a sequence of operations relating to application of cosmetic products on a facial region of the beauty advisor. The media casting device detects a corresponding timestamp for each operation and detects a position of a cosmetic product with respect to facial feature points of the beauty advisor during each of the sequence of operations. The media casting device detects a cosmetic product utilized by the beauty advisor during each of the sequence of operations and generates metadata comprising the sequence of operations, the position of each cosmetic product, the corresponding timestamps, and each detected cosmetic product. The media casting device then transmits the metadata to a client device.
    Type: Application
    Filed: August 24, 2021
    Publication date: March 3, 2022
    Inventor: Teng-Yuan HSIAO