Abstract: A structure includes a semiconductor substrate; a plurality of first dielectric layers at a top side of the substrate; an active device layer at a top side of the first layers; a plurality of second dielectric layers at a top side of the device layer; first and second sense pads; and a metal body that electrically connects the pads. The metal body includes a first portion that is embedded in the first layers, made of a first plurality of discrete segments; a second portion that is embedded in the second layers, made of a second plurality of discrete segments, of which a first is electrically connected to the first pad and a second is electrically connected to the second pad; and a plurality of vias that interconnect the first and second portions. Breaking any of the vias reduces the electrical connectivity between the pads.

Abstract: A semiconductor cell comprises a top FET that contains a first set of silicon nanosheets and a bottom FET that contains a second set of silicon nanosheets. The top FET and bottom FET are in a stacked profile. The semiconductor cell comprises a top FET cutout region lateral to the first set of nanosheets and above a portion of the second set of nanosheets. The semiconductor cell also comprises a dielectric fill within the top FET cutout region.

Abstract: A semiconductor device includes a device under test, and a protection circuit electrically connected to the device under test, the protection circuit including: a protective diode, and a laser fuse configured to, upon receiving a laser pulse via an opening, break an electrical path of the protective diode and he device under test.

Abstract: A microelectronic structure including a nanosheet transistor that includes a source/drain. A frontside contact that includes a first section located on the frontside of the source/drain and a via section that extends to the backside of the nanosheet transistor. A shallow isolation layer located around a portion of the via section the first frontside contact. A backside metal line located on a backside surface of the via section and located on a backside surface of the shallow trench isolation layer. A dielectric liner located along a sidewall of the backside metal line and located along a bottom surface of the backside metal line.

Abstract: A method including forming an oxide layer on a first substrate and forming a second substrate on the oxide layer. Doping a first section of the second substrate while not doping a second section of the second substrate. Forming a first nano device on the second section of the second substrate and forming a second nano device on first section of the second substrate. Flipping the first substrate over to allow for backside processing of the substrate and forming at least one backside contact connected to the first nano device while backside contacts are not formed or connected to the second nano device.

Abstract: An integrated circuit is presented including a protection diode including a plurality of first gates and a plurality of first source/drain (S/D) contacts and a device under test (DUT) including a plurality of second gates and a plurality of second S/D contacts, the DUT being electrically connected to the protection diode by either at least one gate contact or at least on CA contact or at least one buried power rail (BPR). The protection diode is electrically connected to the DUT by middle-of-line (MOL) layers for gate oxide protection before M1 formation.

Abstract: A semiconductor structure including a stacked FET vertical diode is provided. The stacked FET vertical diode includes vertically stacked source/drain regions of opposite conductivity that are electrically connected by a semiconductor material layer that is positioned between the vertically stacked source/drain regions.

Abstract: A semiconductor device includes a device under test, and a protection circuit electrically connected to the device under test, the protection circuit including: a protective diode, and a laser fuse configured to, upon receiving a laser pulse via an opening, break an electrical path of the protective diode and he device under test.

Abstract: A high aspect ratio contact structure formed within a dielectric material includes a top portion and a bottom portion. The top portion of the contact structure includes a tapering profile towards the bottom portion. A first metal stack surrounded by an inner spacer is located within the top portion of the contact structure and a second metal stack is located within the bottom portion of the contact structure. A width of the bottom portion of the contact structure is greater than a minimum width of the top portion of the contact structure.

Abstract: A set of transistor elements includes a substrate of a first doping type and a first well and a second well, both of a second doping type and both formed on the substrate. The set of transistor elements also includes a first complementary transistor cell and a second complementary transistor cell. The set of transistor element also includes an anti-propagation region of the first doping type between the first well and the second well.

Abstract: A semiconductor cell comprises a top FET that contains a first set of silicon nanosheets and a bottom FET that contains a second set of silicon nanosheets. The top FET and bottom FET are in a stacked profile. The semiconductor cell comprises a top FET cutout region lateral to the first set of nanosheets and above a portion of the second set of nanosheets. The semiconductor cell also comprises a dielectric fill within the top FET cutout region.

Abstract: A structure includes a semiconductor substrate; a plurality of first dielectric layers at a top side of the substrate; an active device layer at a top side of the first layers; a plurality of second dielectric layers at a top side of the device layer; first and second sense pads; and a metal body that electrically connects the pads. The metal body includes a first portion that is embedded in the first layers, made of a first plurality of discrete segments; a second portion that is embedded in the second layers, made of a second plurality of discrete segments, of which a first is electrically connected to the first pad and a second is electrically connected to the second pad; and a plurality of vias that interconnect the first and second portions. Breaking any of the vias reduces the electrical connectivity between the pads.

Abstract: An exemplary structure includes a semiconductor substrate; a plurality of first dielectric layers at a top side of the substrate; an active device layer at a top side of the first dielectric layers; a plurality of second dielectric layers at a top side of the active device layer; and a metal body. The body includes a first portion that is embedded in the plurality of first dielectric layers. The first portion comprises a first layer of first metal. The body further includes a second portion that is embedded in the plurality of second dielectric layers. The second portion comprises a first layer of second metal. A plurality of vias interconnect the first portion to the second portion through the active device layer. The first layer of the first portion mechanically connects the plurality of vias and the first layer of the second portion mechanically connects the plurality of vias.

Abstract: A structure includes a semiconductor substrate; a plurality of first dielectric layers at a top side of the substrate; an active device layer at a top side of the first layers; a plurality of second dielectric layers at a top side of the device layer; first and second sense pads at a top side of the second layers; a first metal body electrically connected to the first pad; and a second metal body electrically connected to the second pad. The bodies, with the layers, form a capacitor that couples the pads. Each of the bodies includes: an upper portion that is embedded in the plurality of second layers and is directly connected to a respective one of the first and second pads; a lower portion that is embedded in the plurality of first layers; and a via that connects the upper to the lower portion through the active layer.

Abstract: A structure includes a semiconductor substrate; a plurality of first dielectric layers at a top side of the semiconductor substrate; an active device layer at a top side of the plurality of first dielectric layers; and a plurality of second dielectric layers at a top side of the active device layer. Also included are at least hundreds of metal bodies, each of which is on the order of about 10 nm to about 1000 nm in critical dimension and includes: a first metal plate, at a first level in the plurality of first dielectric layers that is adjacent to the active device layer; a second metal plate, at a second level in the plurality of second dielectric layers that is adjacent to the active device layer; and a first plurality of vias that connect the first metal plate to the second metal plate through the active device layer.

Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor device comprising: a back end of the line (BEOL) stack including a dielectric stack, and an active device region in the dielectric stack, the active device region including at least one component selected from the group consisting of transistors, capacitors and nanosheet structures; and a crack stop that extends vertically through the active device region.

Abstract: Apparatus for mitigating latch-up within semiconductor devices. A semiconductor device includes a first conductor, a second conductor, and a first gate conductor. The first conductor extends in a first direction, receives a first power supply signal, and is connected to a first electrode. The second conductor extends in the first direction, receives a second power supply signal different from the first power supply signal, and is connected to a second electrode. The first conductor is offset from the second conductor in a second direction perpendicular to the first direction in a top-down view to mitigate formation of parasitic devices within the semiconductor device electrically connecting the first conductor with the second conductor. The first gate conductor is disposed adjacent to the first conductor and the second conductor, is disposed on the first electrode and the second electrode, and receives an input signal.

Abstract: A microelectronic structure including a logic device and a passive device. The passive device includes a doped substrate, a silicide layer located on a backside surface of the doped substrate, and a metal plane located on a backside surface of the silicide layer.

Abstract: A microelectronic structure including a nanosheet transistor that includes a source/drain. A frontside contact that includes a first section located on the frontside of the source/drain and a via section that extends to the backside of the nanosheet transistor. A shallow isolation layer located around a portion of the via section the first frontside contact. A backside metal line located on a backside surface of the via section and located on a backside surface of the shallow trench isolation layer. A dielectric liner located along a sidewall of the backside metal line and located along a bottom surface of the backside metal line.

Abstract: A semiconductor structure is provided including stacked first and second devices wherein at least one of the stacked devices includes a lateral diode. The lateral diode includes a p-doped region as an anode, an n-doped region as a cathode and a semiconductor channel material region sandwiched between the anode and the cathode.