Patents by Inventor Terence Hook

Terence Hook has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230378258
    Abstract: A method including forming an oxide layer on a first substrate and forming a second substrate on the oxide layer. Doping a first section of the second substrate while not doping a second section of the second substrate. Forming a first nano device on the second section of the second substrate and forming a second nano device on first section of the second substrate. Flipping the first substrate over to allow for backside processing of the substrate and forming at least one backside contact connected to the first nano device while backside contacts are not formed or connected to the second nano device.
    Type: Application
    Filed: May 17, 2022
    Publication date: November 23, 2023
    Inventors: Ruilong Xie, Anthony I. Chou, Brent A. Anderson, John Christopher Arnold, Junli Wang, Kai Zhao, Terence Hook, Julien Frougier, Xuefeng Liu
  • Publication number: 20230317802
    Abstract: A high aspect ratio contact structure formed within a dielectric material includes a top portion and a bottom portion. The top portion of the contact structure includes a tapering profile towards the bottom portion. A first metal stack surrounded by an inner spacer is located within the top portion of the contact structure and a second metal stack is located within the bottom portion of the contact structure. A width of the bottom portion of the contact structure is greater than a minimum width of the top portion of the contact structure.
    Type: Application
    Filed: March 29, 2022
    Publication date: October 5, 2023
    Inventors: Junli Wang, Brent A Anderson, Terence Hook, Indira Seshadri, Albert M. Young, Stuart Sieg, Su Chen Fan, Shogo Mochizuki
  • Publication number: 20230317722
    Abstract: A set of transistor elements includes a substrate of a first doping type and a first well and a second well, both of a second doping type and both formed on the substrate. The set of transistor elements also includes a first complementary transistor cell and a second complementary transistor cell.
    Type: Application
    Filed: March 24, 2022
    Publication date: October 5, 2023
    Inventor: Terence Hook
  • Publication number: 20230307363
    Abstract: Apparatus for mitigating latch-up within semiconductor devices. A semiconductor device includes a first conductor, a second conductor, and a first gate conductor. The first conductor extends in a first direction, receives a first power supply signal, and is connected to a first electrode. The second conductor extends in the first direction, receives a second power supply signal different from the first power supply signal, and is connected to a second electrode. The first conductor is offset from the second conductor in a second direction perpendicular to the first direction in a top-down view to mitigate formation of parasitic devices within the semiconductor device electrically connecting the first conductor with the second conductor. The first gate conductor is disposed adjacent to the first conductor and the second conductor, is disposed on the first electrode and the second electrode, and receives an input signal.
    Type: Application
    Filed: March 24, 2022
    Publication date: September 28, 2023
    Inventors: David WOLPERT, Leon SIGAL, Terence HOOK
  • Patent number: 11663391
    Abstract: Aspects of the invention include systems and methods for implementing a CMOS circuit design that uses a sea-of-gates fill methodology to provide latch-up avoidance. A non-limiting example computer-implemented method includes identifying a fill cell in the circuit design. The fill cell can include a power rail, a ground rail, and a field-effect transistor (FET) electrically coupled to the power rail through a via. The method can include disconnecting the via from the power rail and moving the via to a disconnected node in the fill cell. Moving the via decouples a source or drain of the fill cell from a well of the fill cell, preventing latch-up while maintaining via and metal shape density.
    Type: Grant
    Filed: August 25, 2021
    Date of Patent: May 30, 2023
    Assignee: International Business Machines Corporation
    Inventors: David Wolpert, Ryan Michael Kruse, Leon Sigal, Richard Edward Serton, Matthew Stephen Angyal, Terence Hook, Richard Andre Wachnik
  • Publication number: 20230062945
    Abstract: Aspects of the invention include systems and methods for implementing a CMOS circuit design that uses a sea-of-gates fill methodology to provide latch-up avoidance. A non-limiting example computer-implemented method includes identifying a fill cell in the circuit design. The fill cell can include a power rail, a ground rail, and a field-effect transistor (FET) electrically coupled to the power rail through a via. The method can include disconnecting the via from the power rail and moving the via to a disconnected node in the fill cell. Moving the via decouples a source or drain of the fill cell from a well of the fill cell, preventing latch-up while maintaining via and metal shape density.
    Type: Application
    Filed: August 25, 2021
    Publication date: March 2, 2023
    Inventors: David Wolpert, Ryan Michael Kruse, Leon Sigal, Richard Edward Serton, Matthew Stephen Angyal, Terence Hook, Richard Andre Wachnik
  • Patent number: 11469146
    Abstract: In a self-aligned fin cut process for fabricating integrated circuits, a sacrificial gate or an epitaxially-formed source/drain region is used as an etch mask in conjunction with a fin cut etch step to remove unwanted portions of the fins. The process eliminates use of a lithographically-defined etch mask to cut the fins, which enables precise and accurate alignment of the fin cut.
    Type: Grant
    Filed: February 8, 2021
    Date of Patent: October 11, 2022
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Lei L. Zhuang, Balasubramanian Pranatharthiharan, Lars Liebmann, Ruilong Xie, Terence Hook
  • Patent number: 11245020
    Abstract: One example of an apparatus includes a conducting channel region. The conducting channel region includes a plurality of epitaxially grown, in situ doped conducting channels arranged in a spaced apart relation relative to each other. A source positioned at a first end of the conducting channel region, and a drain positioned at a second end of the conducting channel region. A gate surrounds all sides of the conducting channel region and fills in spaces between the plurality of epitaxially grown, in situ doped conducting channels.
    Type: Grant
    Filed: January 16, 2020
    Date of Patent: February 8, 2022
    Assignee: International Business Machines Corporation
    Inventors: Ruqiang Bao, Michael A. Guillorn, Terence Hook, Robert R. Robison, Reinaldo Vega, Tenko Yamashita
  • Publication number: 20210183709
    Abstract: In a self-aligned fin cut process for fabricating integrated circuits, a sacrificial gate or an epitaxially-formed source/drain region is used as an etch mask in conjunction with a fin cut etch step to remove unwanted portions of the fins. The process eliminates use of a lithographically-defined etch mask to cut the fins, which enables precise and accurate alignment of the fin cut.
    Type: Application
    Filed: February 8, 2021
    Publication date: June 17, 2021
    Inventors: Lei L. Zhuang, Balasubramanian Pranatharthiharan, Lars Liebmann, Ruilong Xie, Terence Hook
  • Patent number: 10916478
    Abstract: In a self-aligned fin cut process for fabricating integrated circuits, a sacrificial gate or an epitaxially-formed source/drain region is used as an etch mask in conjunction with a fin cut etch step to remove unwanted portions of the fins. The process eliminates use of a lithographically-defined etch mask to cut the fins, which enables precise and accurate alignment of the fin cut.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: February 9, 2021
    Assignee: GLOBALFOUNDRIES U.S. Inc.
    Inventors: Lei L. Zhuang, Balasubramanian Pranatharthiharan, Lars Liebmann, Ruilong Xie, Terence Hook
  • Publication number: 20200258995
    Abstract: One example of an apparatus includes a conducting channel region. The conducting channel region includes a plurality of epitaxially grown, in situ doped conducting channels arranged in a spaced apart relation relative to each other. A source positioned at a first end of the conducting channel region, and a drain positioned at a second end of the conducting channel region. A gate surrounds all sides of the conducting channel region and fills in spaces between the plurality of epitaxially grown, in situ doped conducting channels.
    Type: Application
    Filed: April 22, 2020
    Publication date: August 13, 2020
    Inventors: Ruqiang Bao, Michael A. Guillorn, Terence Hook, Robert R. Robison, Reinaldo Vega, Tenko Yamashita
  • Publication number: 20200251568
    Abstract: One example of an apparatus includes a conducting channel region. The conducting channel region includes a plurality of epitaxially grown, in situ doped conducting channels arranged in a spaced apart relation relative to each other. A source positioned at a first end of the conducting channel region, and a drain positioned at a second end of the conducting channel region. A gate surrounds all sides of the conducting channel region and fills in spaces between the plurality of epitaxially grown, in situ doped conducting channels.
    Type: Application
    Filed: January 16, 2020
    Publication date: August 6, 2020
    Inventors: Ruqiang Bao, Michael A. Guillorn, Terence Hook, Robert R. Robison, Reinaldo Vega, Tenko Yamashita
  • Patent number: 10586854
    Abstract: One example of an apparatus includes a conducting channel region. The conducting channel region includes a plurality of epitaxially grown, in situ doped conducting channels arranged in a spaced apart relation relative to each other. A source positioned at a first end of the conducting channel region, and a drain positioned at a second end of the conducting channel region. A gate surrounds all sides of the conducting channel region and fills in spaces between the plurality of epitaxially grown, in situ doped conducting channels.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: March 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruqiang Bao, Michael A. Guillorn, Terence Hook, Robert R. Robison, Reinaldo Vega, Tenko Yamashita
  • Publication number: 20190259670
    Abstract: In a self-aligned fin cut process for fabricating integrated circuits, a sacrificial gate or an epitaxially-formed source/drain region is used as an etch mask in conjunction with a fin cut etch step to remove unwanted portions of the fins. The process eliminates use of a lithographically-defined etch mask to cut the fins, which enables precise and accurate alignment of the fin cut.
    Type: Application
    Filed: February 20, 2018
    Publication date: August 22, 2019
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Lei L. Zhuang, Balasubramanian Pranatharthiharan, Lars Liebmann, Ruilong Xie, Terence Hook
  • Patent number: 10128347
    Abstract: One example of an apparatus includes a conducting channel region. The conducting channel region includes a plurality of epitaxially grown, in situ doped conducting channels arranged in a spaced apart relation relative to each other. A source positioned at a first end of the conducting channel region, and a drain positioned at a second end of the conducting channel region. A gate surrounds all sides of the conducting channel region and fills in spaces between the plurality of epitaxially grown, in situ doped conducting channels.
    Type: Grant
    Filed: January 4, 2017
    Date of Patent: November 13, 2018
    Assignee: International Business Machines Corporation
    Inventors: Ruqiang Bao, Michael A. Guillorn, Terence Hook, Robert R. Robison, Reinaldo Vega, Tenko Yamashita
  • Publication number: 20180308945
    Abstract: One example of an apparatus includes a conducting channel region. The conducting channel region includes a plurality of epitaxially grown, in situ doped conducting channels arranged in a spaced apart relation relative to each other. A source positioned at a first end of the conducting channel region, and a drain positioned at a second end of the conducting channel region. A gate surrounds all sides of the conducting channel region and fills in spaces between the plurality of epitaxially grown, in situ doped conducting channels.
    Type: Application
    Filed: May 10, 2018
    Publication date: October 25, 2018
    Inventors: Ruqiang Bao, Michael A. Guillorn, Terence Hook, Robert R. Robison, Reinaldo Vega, Tenko Yamashita
  • Publication number: 20180190782
    Abstract: One example of an apparatus includes a conducting channel region. The conducting channel region includes a plurality of epitaxially grown, in situ doped conducting channels arranged in a spaced apart relation relative to each other. A source positioned at a first end of the conducting channel region, and a drain positioned at a second end of the conducting channel region. A gate surrounds all sides of the conducting channel region and fills in spaces between the plurality of epitaxially grown, in situ doped conducting channels.
    Type: Application
    Filed: January 4, 2017
    Publication date: July 5, 2018
    Inventors: Ruqiang Bao, Michael A. Guillorn, Terence Hook, Robert R. Robison, Reinaldo Vega, Tenko Yamashita
  • Publication number: 20080108186
    Abstract: In a method of fabricating a CMOS structure, a bulk device can be formed in a first region in conductive communication with an underlying bulk region of the substrate. A first gate conductor may overlie the first region. An SOI device can be formed which has a source drain conduction path in a SOI layer, i.e., a semiconductor layer that is separated from the bulk region by a buried dielectric region. The crystal orientations of the SOI layer and the bulk region can be different. A first diode can be formed in a second region of the substrate in conductive communication with the bulk region. The first diode may be connected in a reverse-biased orientation to a first gate conductor above the SOI layer, such that a voltage on the gate conductor that exceeds the breakdown voltage can be discharged through the first diode to the bulk region of the substrate. A second diode may be formed in a third region of the substrate in conductive communication with the bulk region.
    Type: Application
    Filed: December 19, 2007
    Publication date: May 8, 2008
    Inventors: Terence Hook, Anda Mocuta, Jeffrey Sleight, Anthony Stamper
  • Publication number: 20080042798
    Abstract: A resistor with heat sink is provided. The heat sink includes a conductive path having metal or other thermal conductor having a high thermal conductivity. To avoid shorting the electrical resistor to ground with the thermal conductor, a thin layer of high thermal conductivity electrical insulator is interposed between the thermal conductor and the body of the resistor. Accordingly, a resistor can carry large amounts of current because the high conductivity thermal conductor will conduct heat away from the resistor to a heat sink. Various configurations of thermal conductors and heat sinks are provided offering good thermal conductive properties in addition to reduced parasitic capacitances and other parasitic electrical effects, which would reduce the high frequency response of the electrical resistor.
    Type: Application
    Filed: August 31, 2007
    Publication date: February 21, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Douglas Coolbaugh, Ebenezer Eshun, Terence Hook, Robert Rassel, Edmund Sprogis, Anthony Stamper, William Murphy
  • Publication number: 20080022237
    Abstract: A method for calibrating a software model for a given structure of interest for a variable imposed by an adjacent structure. First determine the spatial extent of the variable imposed by the adjacent structure. Then assign a value to the spatial extent, which varies as a function of distance from the adjacent structure to the given structure. Finally, attach that value to the model of the given structure.
    Type: Application
    Filed: October 3, 2007
    Publication date: January 24, 2008
    Inventors: Eric Adler, Serge Biesemans, Micah Galland, Terence Hook, Judith McCullen, Eric Phipps, James Slinkman