Patents by Inventor Terence Hook
Terence Hook has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20080018378Abstract: A circuit having a precision passive circuit element, such as a resistor or a capacitor, with a target value of an electrical parameter is fabricated on a substrate with a plurality of independent parallel-connected passive circuit elements. The plurality of passive circuit elements are designed to have a plurality of values of the electrical parameter which are spaced or offset at or around the target value of the electrical parameter, such as three circuit elements with one having a value at the target value, one having a value above the target value, and one having a value below the target value. Each passive circuit element also has a fuse in series therewith. A reference calibration structure is also fabricated, which can be a passive circuit element having the target value of the electrical parameter, in a reference area of the substrate under the same conditions and at the same time as fabrication of the plurality of passive circuit elements.Type: ApplicationFiled: October 1, 2007Publication date: January 24, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Douglas Coolbaugh, Hayden Cranford, Terence Hook, Anthony Stamper
-
Publication number: 20080019101Abstract: A resistor with heat sink is provided. The heat sink includes a conductive path having metal or other thermal conductor having a high thermal conductivity. To avoid shorting the electrical resistor to ground with the thermal conductor, a thin layer of high thermal conductivity electrical insulator is interposed between the thermal conductor and the body of the resistor. Accordingly, a resistor can carry large amounts of current because the high conductivity thermal conductor will conduct heat away from the resistor to a heat sink. Various configurations of thermal conductors and heat sinks are provided offering good thermal conductive properties in addition to reduced parasitic capacitances and other parasitic electrical effects, which would reduce the high frequency response of the electrical resistor.Type: ApplicationFiled: July 13, 2007Publication date: January 24, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Douglas COOLBAUGH, Ebenezer ESHUN, Terence HOOK, Robert RASSEL, Edmund SPROGIS, Anthony STAMPER, William MURPHY
-
Publication number: 20070228479Abstract: A chip includes a CMOS structure having a bulk device disposed in a first region of a semiconductor substrate in conductive communication with an underlying bulk region of the substrate, the first region and the bulk region having a first crystal orientation. A SOI device is disposed in a semiconductor-on-insulator (“SOI”) layer separated from the bulk region of the substrate by a buried dielectric layer, the SOI layer having a different crystal orientation from the first crystal orientation. In one example, the bulk device includes a p-type field effect transistor (“PFET”) and the SOI device includes an n-type field effect transistor (“NFET”) device. Alternatively, the bulk device can include an NFET and the SOI device can include a PFET. When the SOI device has a gate conductor in conductive communication with a gate conductor of the bulk device, charging damage can occur to the SOI device, except for the presence of diodes in reverse-biased conductive communication with the bulk region.Type: ApplicationFiled: March 31, 2006Publication date: October 4, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Terence Hook, Anda Mocuta, Jeffrey Sleight, Anthony Stamper
-
Publication number: 20070212799Abstract: Disclosed is a method for preventing charging damage in an integrated circuit design, for example, a design having silicon over insulator (SOI) transistors. The method/circuit prevents damage from charging during processing to the gate of IC devices by assigning regions to the IC design such that the devices located within the regions have electrically independent nets, identifying devices that may have a voltage differential between the source/drain and gate as susceptible devices within a given region, and connecting a element across the source/drain and the gate of each of the susceptible devices such that the element is positioned within the region. Alternatively, the method/circuit provides for connecting compensating conductors to an element to eliminate potential charging damage.Type: ApplicationFiled: May 17, 2007Publication date: September 13, 2007Inventors: Terence Hook, Jeffrey Zimmerman
-
Publication number: 20070045749Abstract: A method for forming a CMOS well structure including forming a plurality of first conductivity type wells over a substrate, each of the plurality of first conductivity type wells formed in a respective opening in a first mask. A cap is formed over each of the first conductivity type wells, and the first mask is removed. Sidewall spacers are formed on sidewalls of each of the first conductivity type wells. A plurality of second conductivity type wells are formed, each of the plurality of second conductivity type wells are formed between respective first conductivity type wells. A plurality of shallow trench isolations are formed between the first conductivity type wells and second conductive type wells. The plurality of first conductivity type wells are formed by a first selective epitaxial growth process, and the plurality of second conductivity type wells are formed by a second selective epitaxial growth process.Type: ApplicationFiled: October 23, 2006Publication date: March 1, 2007Inventors: Wilfried Haensch, Terence Hook, Louis Hsu, Rajiv Joshi, Werner Rausch
-
Publication number: 20070040277Abstract: A method and structure for suppressing localized metal precipitate formation (LMPF) in semiconductor processing. For each metal wire that is exposed to the manufacturing environment and is electrically coupled to an N region, at least one P+ region is formed electrically coupled to the same metal wire. As a result, few excess electrons are available to combine with metal ions to form localized metal precipitate at the metal wire. A monitoring ramp terminal can be formed around and electrically disconnected from the metal wire. By applying a voltage difference to the metal wire and the monitoring ramp terminal and measuring the resulting current flowing through the metal wire and the monitoring ramp terminal, it can be determined whether localized metal precipitate is formed at the metal wire.Type: ApplicationFiled: October 19, 2006Publication date: February 22, 2007Inventors: Jonathan Chapple-Sokol, Terence Hook, Baozhen Li, Thomas McDevitt, Christopher Ponsolle, Bette Reuter, Timothy Sullivan, Jeffrey Zimmerman
-
Publication number: 20060208323Abstract: A semiconductor device and a method of fabricating the semiconductor device, the semiconductor device including: one or more FETs of a first polarity and one or more FETs of a second and opposite polarity, at least one of the one or more FETs of the first polarity having a gate dielectric having a thickness different from a thickness of a gate dielectric of at least one of the one or more FETs of the second polarity.Type: ApplicationFiled: May 2, 2006Publication date: September 21, 2006Applicant: International Business Machines CorporationInventors: Brent Anderson, Terence Hook
-
Publication number: 20060205098Abstract: A process is provided for determining the effects of scattering from the edge of a resist during a doping process. Edges of a resist which has been patterned to create an n-well are simulated and individually stepped across a predetermined region in predetermined step sizes. The step sizes may vary from step to step after each step, the scattering effects due to the resist edge at its particular location is determined. A resist of virtually any shape may be divided into its component edges and each edge may be individually stepped during the process.Type: ApplicationFiled: March 8, 2005Publication date: September 14, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Micah Galland, Terence Hook
-
Publication number: 20060157799Abstract: A field effect transistor with associated parasitic lateral npn bipolar junction transistor includes a source region in a substrate, a channel region in the substrate laterally adjacent to the source region, a drain region in the substrate laterally adjacent to the channel region, and a gate above the channel region of the substrate. In addition, a reduced trigger voltage region of the substrate is positioned below the drain region. The reduced trigger voltage region has a threshold voltage of about zero and comprises an undoped region of the pure wafer substrate. Thus, the reduced trigger voltage region is free of implanted N-type and P-type doping.Type: ApplicationFiled: January 17, 2005Publication date: July 20, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kiran Chatty, Robert Gauthier, Terence Hook, Christopher Putnam, Mujahid Muhammad
-
Publication number: 20060152333Abstract: A resistor with heat sink is provided. The heat sink includes a conductive path having metal or other thermal conductor having a high thermal conductivity. To avoid shorting the electrical resistor to ground with the thermal conductor, a thin layer of high thermal conductivity electrical insulator is interposed between the thermal conductor and the body of the resistor. Accordingly, a resistor can carry large amounts of current because the high conductivity thermal conductor will conduct heat away from the resistor to a heat sink. Various configurations of thermal conductors and heat sinks are provided offering good thermal conductive properties in addition to reduced parasitic capacitances and other parasitic electrical effects, which would reduce the high frequency response of the electrical resistor.Type: ApplicationFiled: January 10, 2005Publication date: July 13, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Douglas Coolbaugh, Ebenezer Eshun, Terence Hook, Robert Rassel, Edmund Sprogis, Anthony Stamper, William Murphy
-
Publication number: 20060086984Abstract: Disclosed is a method and circuit for preventing charging damage in an integrated circuit design, for example, a design having silicon over insulator (SOI) transistors. The method/circuit prevents damage from charging during processing to the gate of IC devices by assigning regions to the IC design such that the devices located within the regions have electrically independent nets, identifying devices that may have a voltage differential between the source/drain and gate as susceptible devices within a given region, and connecting a element across the source/drain and the gate of each of the susceptible devices such that the element is positioned within the region. Alternatively, the method/circuit provides for connecting compensating conductors to an element to eliminate potential charging damage.Type: ApplicationFiled: January 9, 2006Publication date: April 27, 2006Inventors: Terence Hook, Jeffery Zimmerman
-
Publication number: 20050280097Abstract: A semiconductor device and a method of fabricating the semiconductor device, the semiconductor device including: one or more FETs of a first polarity and one or more FETs of a second and opposite polarity, at least one of the one or more FETs of the first polarity having a gate dielectric having a thickness different from a thickness of a gate dielectric of at least one of the one or more FETs of the second polarityType: ApplicationFiled: June 21, 2004Publication date: December 22, 2005Inventors: Brent Anderson, Terence Hook
-
Publication number: 20050233478Abstract: A circuit having a precision passive circuit element, such as a resistor or a capacitor, with a target value of an electrical parameter is fabricated on a substrate with a plurality of independent parallel-connected passive circuit elements. The plurality of passive circuit elements are designed to have a plurality of values of the electrical parameter which are spaced or offset at or around the target value of the electrical parameter, such as three circuit elements with one having a value at the target value, one having a value above the target value, and one having a value below the target value. Each passive circuit element also has a fuse in series therewith. A reference calibration structure is also fabricated, which can be a passive circuit element having the target value of the electrical parameter, in a reference area of the substrate under the same conditions and at the same time as fabrication of the plurality of passive circuit elements.Type: ApplicationFiled: April 14, 2004Publication date: October 20, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Douglas Coolbaugh, Hayden Cranford, Terence Hook, Anthony Stamper
-
Publication number: 20050194689Abstract: A method and structure for suppressing localized metal precipitate formation (LMPF) in semiconductor processing. For each metal wire that is exposed to the manufacturing environment and is electrically coupled to an N region, at least one P+ region is formed electrically coupled to the same metal wire. As a result, few excess electrons are available to combine with metal ions to form localized metal precipitate at the metal wire. A monitoring ramp terminal can be formed around and electrically disconnected from the metal wire. By applying a voltage difference to the metal wire and the monitoring ramp terminal and measuring the resulting current flowing through the metal wire and the monitoring ramp terminal, it can be determined whether localized metal precipitate is formed at the metal wire.Type: ApplicationFiled: March 6, 2004Publication date: September 8, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jonathan Chapple-Sokol, Terence Hook, Baozhen Li, Thomas McDevitt, Christopher Ponsolle, Bette Reuter, Timothy Sullivan, Jeffrey Zimmerman
-
Publication number: 20050167786Abstract: A method and system for forming a semiconductor device having superior ESD protection characteristics. A resistive material layer is disposed within a contact hole on at least one of the contact stud upper and lower surface. In preferred embodiments, the integral resistor has a resistance value of between about one Ohm and about ten Ohms, or between 10 and 100 Ohms. Embodiments of the resistive layer include sputtered silicon material, a tunnel oxide, a tunnel nitride, a silicon-implanted oxide, a silicon-implanted nitride, or an amorphous polysilicon. Embodiments of the invention include SRAMs, bipolar transistors, SOI lateral diodes, MOSFETs and SiGe Transistors.Type: ApplicationFiled: February 3, 2004Publication date: August 4, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jason Gill, Terence Hook, Randy Mann, William Murphy, William Tonti, Steven Voldman
-
Publication number: 20050110535Abstract: A circuit, including: a capacitor coupled between a first circuit node and a second circuit node and that leaks a leakage current from the first circuit node to the second circuit node; and a compensation circuit adapted to supply a compensatory current to compensate for the leakage current to the first circuit node.Type: ApplicationFiled: November 21, 2003Publication date: May 26, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kerry Bernstein, Anthony Bonaccio, John Fifield, Allen Haar, Shiu Ho, Terence Hook, Michael Sorna, Stephen Wyatt
-
Publication number: 20050106800Abstract: A method for forming a CMOS well structure including forming a plurality of first conductivity type wells over a substrate, each of the plurality of first conductivity type wells formed in a respective opening in a first mask. A cap is formed over each of the first conductivity type wells, and the first mask is removed. Sidewall spacers are formed on sidewalls of each of the first conductivity type wells. A plurality of second conductivity type wells are formed, each of the plurality of second conductivity type wells are formed between respective first conductivity type wells. A plurality of shallow trench isolations are formed between the first conductivity type wells and second conductive type wells. The plurality of first conductivity type wells are formed by a first selective epitaxial growth process, and the plurality of second conductivity type wells are formed by a second selective epitaxial growth process.Type: ApplicationFiled: November 14, 2003Publication date: May 19, 2005Applicant: International Business Machines CorporationInventors: Wilfried Haensch, Terence Hook, Louis Hsu, Rajiv Joshi, Werner Rausch
-
Publication number: 20050098799Abstract: Disclosed is a method and structure for altering an integrated circuit design having silicon over insulator (SOI) transistors. The method/structure prevents damage from charging during processing to the gate of SOI transistors by tracing electrical nets in the integrated circuit design, identifying SOI transistors that may have a voltage differential between the source/drain and gate as potentially damaged SOI transistors (based on the tracing of the electrical nets), and connecting a shunt device across the source/drain and the gate of each of the potentially damaged SOI transistors. Alternatively, the method/structure provides for connecting compensating conductors through a series device.Type: ApplicationFiled: December 4, 2004Publication date: May 12, 2005Inventors: Henry Bonges, David Harmon, Terence Hook, Wing Lai
-
Publication number: 20050093072Abstract: A method and structure alters an integrated circuit design having silicon over insulator (SOI) transistors. The method/structure prevents damage from charging during processing to the gate of SOI transistors by tracing electrical nets in the integrated circuit design, identifying SOI transistors that have a voltage differential between the source/drain and gate as potentially damaged SOI transistors (based on the tracing of the electrical nets), and connecting a shunt device across the source/drain and the gate of each of the potentially damaged SOI transistors. Alternatively, the method/structure provides for connecting compensating conductors through a series device.Type: ApplicationFiled: November 4, 2003Publication date: May 5, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Henry Bonges, David Harmon, Terence Hook, Wing Lai