Abstract: A synchronous dynamic random access memory ("SDRAM") operates with matching read and write latencies. To prevent data collision at the memory array, the SDRAM includes interim address and interim data registers that temporarily store write addresses and input data until an available interval is located where no read data or read addresses occupy the memory array. During the available interval, data is transferred from the interim data register to a location in the memory array identified by the address in the interim array register. In one embodiment, the SDRAM also includes address and compare logic to prevent reading incorrect data from an address to which the proper data has not yet been written. In another embodiment, a system controller monitors commands and addresses and inserts no operation commands to prevent such collision of data and addresses.

Abstract: A system for supporting integrated circuit packages to prevent mechanical failure of the packages at their connection to a printed circuit board or card involves bracing the packages to the board or card. The packages may also be braced against one another. The structure is particularly well adapted to supporting vertical surface mount packages at a point spaced from the point where they connect to a printed circuit board or card.

Abstract: A differential transistor pair is used for a Low Voltage Transistor-Transistor Logic (LVTTL) input buffer to provide an input buffer for a modified and enhanced LVTTL specification. The differential input buffer accurately detects high and low voltages which are respectively lower and higher than existing specified LVTTL voltage levels, yet provides output voltages that are representative of intended logic levels. This provides the ability to use the improved input buffer with existing drivers at higher frequencies where the voltage swing provided by the existing drivers do not produce as large a voltage swing as that required by existing LVTTL specifications.

Abstract: A semiconductor die assembly employing a voltage reference plane structure electrically isolated from, but in immediate proximity to, leads of a lead frame to which the die is electrically connected. A non-conductive adhesive or an adhesively-coated dielectric film is used to position the voltage reference plane on the leads. The voltage reference plane is electrically connected to a ground or other reference potential pin of the die through a connection to one of the leads. The assembly is encapsulated, preferably by transfer-molding of a filled polymer. More than one discrete voltage reference plane structure may be employed, for example, when the package is of an LOC configuration with two rows of leads, each having a voltage reference plane secured thereto, or a single voltage reference plane including major portions adhered to leads and interposed connection portions may be applied to all of the leads of an assembly.

Abstract: A system for supporting integrated circuit packages to prevent mechanical failure of the packages at their connection to a printed circuit board or card involves bracing the packages to the board or card. The packages may also be braced against one another. The structure is particularly well adapted to supporting vertical surface mount packages at a point spaced from the point where they connect to a printed circuit board or card.

Abstract: A system for supporting integrated circuit packages to prevent mechanical failure of the packages at their connection to a printed circuit board or card involves bracing the packages to the board or card. The packages may also be braced against one another. The structure is particularly well adapted to supporting vertical surface mount packages at a point spaced from the point where they connect to a printed circuit board or card.

Abstract: A memory device includes an output data path that transfers data from an I/O circuit coupled to a memory array to an output tri-state buffer. A comparing circuit compares data from the I/O circuit to a desired data pattern. If the data does not match the desired pattern, the comparing circuit outputs an error signal that is input to the output buffer. When the output buffer receives the error signal, the output buffer is disabled and outputs a tri-state condition on a data bus. Since the error signal corresponds to more than one data bit, the tri-state condition of the output buffer is held for more than one tick of the data clock, rather than only a single tick. Consequently, the tri-state condition remains on the bus for sufficiently long that a test system can detect the tri-state condition even at very high clock frequencies.

Abstract: An integrated circuit having an adjustable delay circuit such that the timing characteristics of the integrated circuit can be adjusted. A method for adjusting the timing characteristics of the integrated circuit in order to insure that the integrated circuit meets the specifications of a lower speed grade in the event that the integrated circuit fails the specifications of a targeted speed grade.

Abstract: An outrigger lowering assembly structured to pivot a fishing pole between a generally lowered and a generally elevated orientation, the assembly including an outrigger engagement hub having a retention segment which receives a fishing pole butt end of the fishing pole securely therein, and a pivot segment supportingly extending from the retention segment into pivoted, supported engagement with a base assembly that is secured to the boat.

Abstract: An outrigger pivot assembly structured to rotatably support an outrigger fishing assembly having a shaft bottom end, the pivot assembly including a support housing coupled to a support surface of a boat and structured to generally receive and support a positioning member therein. The positioning member, which is coupled with the shaft bottom end of the outrigger fishing assembly, is structured to rotate the outrigger fishing assembly upon rotation thereof relative to the support housing. A outrigger pivot assembly further includes a handle assembly structured to rotate the positioning member and outrigger fishing assembly upon pivoted movement thereof about a perimeter of the support housing, and a lock assembly having a channel with at least a first position, a second position and a connection segment wherethrough the handle assembly is structured to selectively move when not being retained in place as a result of a structure of said lock assembly.

Abstract: A differential transistor pair is used for a Low Voltage Transistor-Transistor Logic (LVTTL) input buffer to provide an input buffer for a modified and enhanced LVTTL specification. The differential input buffer accurately detects high and low voltages which are respectively lower and higher than existing specified LVTTL voltage levels, yet provides output voltages that are representative of intended logic levels. This provides the ability to use the improved input buffer with existing drivers at higher frequencies where the voltage swing provided by the existing drivers do not produce as large a voltage swing as that required by existing LVTTL specifications.

Abstract: The invention is a self-terminating helper flip-flop buffer circuit pertinent to a dynamic random access memory (DRAM) or static random access memory (SRAM) device. The invention turns off a device which is sourcing current to pull the data line low. The device is turned off when the potential on the low data line has transitioned to the trip point of the output data latch. The circuit of the invention senses the transition and provides the self terminating signal to the current source.

Abstract: The invention is an apparatus for implementing a split read/write operation in a multiple write enable dynamic random access memory (DRAM) device. A split read/write operation is an operation where the data in at least one bank is read while the data is being written to at least one remaining bank, all banks accessed by the same address. The DRAM device of the invention is also capable of a write to at least one bank and a read to at least one bank. In instances where all of the banks are not written, the banks not being written are refreshed; and in instances where all of the banks are not being read, the banks not being read are masked for a write. The invention also provides individual masking of selected memory arrays in both write and read operations.

Abstract: The invention is a method for implementing a split read/write operation in a multiple write enable dynamic random access memory device. A split read/write operation is an operation where the data in at least one bank is read while the data is being written to at least one remaining bank, all banks accessed by the same address. The method of the invention also implements writes and reads to all of the banks, a write to at least one bank, and a read to at least one bank. In instances where all of the banks are not written, the banks not being written are refreshed; and in instances where all of the banks are not being read, the banks not being read are masked for a write. The invention also provides individual masking of selected memory arrays in both write and read operations.

Abstract: A unique method of testing an integrated circuit DRAM for incorrect stored data is disclosed. A JEDEC test mode entry is initiated by normal means, i.e., Write Enable (WE*) and Column Address Select (CAS*) before Row Address Select (RAS*) with specific address data to select a specific test. Data bits are then loaded in the DRAM cells and column data bits compared. The subarray bits are also compared with bits in an expected data register which has been loaded at the beginning of the read cycle. If column bits match and subarray bits match the expected data register, ones are indicated on the data (out) bus; otherwise, a zero appears in case of a data error.

Abstract: The invention synchronizes the refresh cycles of a bank of self-refreshing DRAMs. The refresh cycles are synchronized through a bidirectional control path from each self-refreshing DRAM to its respective external refresh pin. An arbitration circuit determines the self-refreshing DRAM having a fastest timing sequence, maintains that timing sequence and shuts down all timing circuits having slower timing sequences. The arbitration circuit of each self-refreshing DRAM provides a refresh signal to each respective refresh circuit.

Abstract: The invention is a circuit synchronizing the refresh cycles of a bank of self-refreshing DRAMs. The refresh cycles are synchronized through a bidirectional control path from each self-refreshing DRAM to its respective external refresh pin. An arbitration circuit determines the self-refreshing DRAM having a fastest timing sequence, maintains that timing sequence and shuts down all timing circuits having slower timing sequences. The arbitration circuit of each self-refreshing DRAM provides a refresh signal to each respective refresh circuit.

Abstract: A low noise output buffer circuit that activates and deactivates the output by means of a two stage NAND and FET circuit. The two stages turn on sequentially but turn off simultaneously and minimizes the peak power supply current that normally appears during input and output switching operations.

Abstract: A low-noise output buffer circuit that activates and deactivates the output by means of a two stage NAND and FET circuit, which senses a low voltage in a first stage pull-up (pull-down) NAND output before activating pull-down (pull-up) devices and the second stage, thereby minimizing the power supply current spike that normally appears during input and output switching operations.

Abstract: The invention is a self-terminating helper flip-flop buffer circuit pertinent to a dynamic random access memory (DRAM) or static random access memory (SRAM) device. The invention turns off a device which is sourcing current to pull the data line low. The device is turned off when the potential on the low data line has transitioned to the trip point of the output data latch. The circuit of the invention senses the transition and provides the self terminating signal to the current source.