Patents by Inventor Teruyuki Fujii
Teruyuki Fujii has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11545578Abstract: A semiconductor device with high reliability is provided. The semiconductor device includes a first insulator, a second insulator, and a transistor; the transistor includes an oxide in a channel formation region; the oxide is surrounded by the first insulator; and the first insulator is surrounded by the second insulator. The first insulator includes a region with a lower hydrogen concentration than the second insulator. Alternatively, the first insulator includes a region with a lower hydrogen concentration than the second insulator and with a lower nitrogen concentration than the second insulator.Type: GrantFiled: April 18, 2019Date of Patent: January 3, 2023Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Yasumasa Yamane, Takashi Hirose, Teruyuki Fujii, Hajime Kimura, Daigo Shimada
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Patent number: 10069014Abstract: A base insulating film is formed over a substrate. A first oxide semiconductor film is formed over the base insulating film, and then first heat treatment is performed to form a second oxide semiconductor film. Then, selective etching is performed to form a third oxide semiconductor film. An insulating film is formed over the first insulating film and the third oxide semiconductor film. A surface of the insulating film is polished to expose a surface of the third oxide semiconductor film, so that a sidewall insulating film is formed in contact with at least a side surface of the third oxide semiconductor film. Then, a source electrode and a drain electrode are formed over the sidewall insulating film and the third oxide semiconductor film. A gate insulating film and a gate electrode are formed.Type: GrantFiled: September 22, 2014Date of Patent: September 4, 2018Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Teruyuki Fujii, Sho Nagamatsu
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Patent number: 9935363Abstract: In a semiconductor device in which a copper plating layer is used for a conductor of an antenna and in which an integrated circuit and the antenna are formed over the same substrate, an object is to prevent an adverse effect on electrical characteristics of a circuit element due to diffusion of copper, as well as to provide a copper plating layer with favorable adhesiveness. Another object is to prevent a defect in the semiconductor device that stems from poor connection between the antenna and the integrated circuit, in the semiconductor device in which the integrated circuit and the antenna are formed over the same substrate. In the semiconductor device, a copper plating layer is used for the antenna, an alloy of Ag, Pd, and Cu is used for a seed layer thereof, and TiN or Ti is used for a barrier layer.Type: GrantFiled: March 20, 2014Date of Patent: April 3, 2018Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Teruyuki Fujii, Kazuya Hanaoka
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Patent number: 9917109Abstract: A semiconductor device includes a wiring embedded in an insulating layer, an oxide semiconductor layer over the insulating layer, a source electrode and a drain electrode electrically connected to the oxide semiconductor layer, a gate electrode provided to overlap with the oxide semiconductor layer, and a gate insulating layer provided between the oxide semiconductor layer and the gate electrode. The insulating layer is formed so that part of a top surface of the wiring is exposed. The part of the top surface of the wiring is positioned higher than part of a surface of the insulating layer. The wiring in a region exposed from the insulating layer is electrically connected to the source electrode or the drain electrode. The root-mean-square roughness of a region which is part of the surface of the insulating layer and in contact with the oxide semiconductor layer is 1 nm or less.Type: GrantFiled: March 3, 2011Date of Patent: March 13, 2018Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Teruyuki Fujii, Ryota Imahayashi
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Patent number: 9324773Abstract: One pixel is divided into a first region including a first light emitting element and a second region including a second light emitting element, wherein the first region emits light in one direction and the second region emits light in the direction opposite to that of the first region. Independently driving the first light emitting element and the second light emitting element allows images to be displayed independently on the surface.Type: GrantFiled: October 10, 2014Date of Patent: April 26, 2016Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Teruyuki Fujii, Shunpei Yamazaki
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Patent number: 9112067Abstract: An object relates to an electrode of a semiconductor device or a method for manufacturing a semiconductor device, which includes a bonding step, and problems are: (1) high resistance of a semiconductor device due to the use of an Al electrode, (2) formation of an alloy by Al and Si, (3) high resistance of a film formed by a sputtering method, and (4) defective bonding in a bonding step which is caused if a bonding surface has a large unevenness. A semiconductor device includes a metal substrate or a substrate provided with a metal film, a copper (Cu) plating film over and bonded to the metal substrate or the metal film by employing a thermocompression bonding method, a barrier film over the Cu plating film, a single crystal silicon film over the barrier film, and an electrode layer over the single crystal silicon film.Type: GrantFiled: April 23, 2010Date of Patent: August 18, 2015Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Teruyuki Fujii, Kohei Ohshima, Junya Maruyama, Akihisa Shimomura
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Patent number: 9064827Abstract: An object is to provide a semiconductor device with excellent reproducibility which is manufactured at low cost. A method for manufacturing a semiconductor device includes steps of forming a first electrode over a substrate; forming an insulating layer over the substrate and the first electrode; pressing a mold against the insulating layer to form an opening in the insulating layer; separating the mold from the insulating layer in which opening is formed; hardening the insulating layer in which the opening is formed to form a partition wall; forming a light-emitting layer over the first electrode and the partition wall; and forming a second electrode over the light-emitting layer. As a method for forming the partition wall, nano-imprinting is used. An insulating layer contains polysilane. The partition wall formed of a silicon oxide film is formed by UV light irradiation and heating.Type: GrantFiled: June 4, 2007Date of Patent: June 23, 2015Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Teruyuki Fujii
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Publication number: 20150123101Abstract: One pixel is divided into a first region including a first light emitting element and a second region including a second light emitting element, wherein the first region emits light in one direction and the second region emits light in the direction opposite to that of the first region. Independently driving the first light emitting element and the second light emitting element allows images to be displayed independently on the surface.Type: ApplicationFiled: October 10, 2014Publication date: May 7, 2015Inventors: Teruyuki Fujii, Shunpei Yamazaki
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Publication number: 20150008430Abstract: A base insulating film is formed over a substrate. A first oxide semiconductor film is formed over the base insulating film, and then first heat treatment is performed to form a second oxide semiconductor film. Then, selective etching is performed to form a third oxide semiconductor film. An insulating film is formed over the first insulating film and the third oxide semiconductor film. A surface of the insulating film is polished to expose a surface of the third oxide semiconductor film, so that a sidewall insulating film is formed in contact with at least a side surface of the third oxide semiconductor film. Then, a source electrode and a drain electrode are formed over the sidewall insulating film and the third oxide semiconductor film. A gate insulating film and a gate electrode are formed.Type: ApplicationFiled: September 22, 2014Publication date: January 8, 2015Inventors: Shunpei YAMAZAKI, Teruyuki FUJII, Sho NAGAMATSU
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Patent number: 8865555Abstract: A base insulating film is formed over a substrate. A first oxide semiconductor film is formed over the base insulating film, and then first heat treatment is performed to form a second oxide semiconductor film. Then, selective etching is performed to form a third oxide semiconductor film. An insulating film is formed over the first insulating film and the third oxide semiconductor film. A surface of the insulating film is polished to expose a surface of the third oxide semiconductor film, so that a sidewall insulating film is formed in contact with at least a side surface of the third oxide semiconductor film. Then, a source electrode and a drain electrode are formed over the sidewall insulating film and the third oxide semiconductor film. A gate insulating film and a gate electrode are formed.Type: GrantFiled: January 23, 2012Date of Patent: October 21, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Teruyuki Fujii, Sho Nagamatsu
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Patent number: 8860011Abstract: One pixel is divided into a first region including a first light emitting element and a second region including a second light emitting element, wherein the first region emits light in one direction and the second region emits light in the direction opposite to that of the first region. Independently driving the first light emitting element and the second light emitting element allows images to be displayed independently on the surface.Type: GrantFiled: December 22, 2011Date of Patent: October 14, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Teruyuki Fujii, Shunpei Yamazaki
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Publication number: 20140203978Abstract: In a semiconductor device in which a copper plating layer is used for a conductor of an antenna and in which an integrated circuit and the antenna are formed over the same substrate, an object is to prevent an adverse effect on electrical characteristics of a circuit element due to diffusion of copper, as well as to provide a copper plating layer with favorable adhesiveness. Another object is to prevent a defect in the semiconductor device that stems from poor connection between the antenna and the integrated circuit, in the semiconductor device in which the integrated circuit and the antenna are formed over the same substrate. In the semiconductor device, a copper plating layer is used for the antenna, an alloy of Ag, Pd, and Cu is used for a seed layer thereof, and TiN or Ti is used for a barrier layer.Type: ApplicationFiled: March 20, 2014Publication date: July 24, 2014Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventors: Teruyuki Fujii, Kazuya Hanaoka
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Patent number: 8698697Abstract: In a semiconductor device in which a copper plating layer is used for a conductor of an antenna and in which an integrated circuit and the antenna are formed over the same substrate, an object is to prevent an adverse effect on electrical characteristics of a circuit element due to diffusion of copper, as well as to provide a copper plating layer with favorable adhesiveness. Another object is to prevent a defect in the semiconductor device that stems from poor connection between the antenna and the integrated circuit, in the semiconductor device in which the integrated circuit and the antenna are formed over the same substrate. In the semiconductor device, a copper plating layer is used for the antenna, an alloy of Ag, Pd, and Cu is used for a seed layer thereof, and TiN or Ti is used for a barrier layer.Type: GrantFiled: June 9, 2008Date of Patent: April 15, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Teruyuki Fujii, Kazuya Hanaoka
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Patent number: 8653520Abstract: An object is to provide a semiconductor device having a novel structure in which a transistor including an oxide semiconductor and a transistor including a semiconductor material other than an oxide semiconductor are stacked. The semiconductor device includes a first transistor, an insulating layer over the first transistor, and a second transistor over the insulating layer. In the semiconductor device, the first transistor includes a first channel formation region, the second transistor includes a second channel formation region, the first channel formation region includes a semiconductor material different from a semiconductor material of the second channel formation region, and the insulating layer includes a surface whose root-mean-square surface roughness is less than or equal to 1 nm.Type: GrantFiled: February 4, 2011Date of Patent: February 18, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Teruyuki Fujii, Ryota Imahayashi, Shinya Sasagawa, Motomu Kurata, Fumika Taguchi
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Patent number: 8420409Abstract: An object is to provide a highly reliable semiconductor device that has tolerance to external stress and electrostatic discharge. Another object is to prevent defective shapes and defective characteristics due to the external stress or an electrostatic discharge in the manufacturing process, and to manufacture a semiconductor device with high yield. Still another object is to manufacture a semiconductor device at low cost and with high productivity. With the use of a conductive shield, electrostatic breakdown (malfunctions of the circuit or damages of a semiconductor element) due to electrostatic discharge of the semiconductor integrated circuit is prevented. The conductive shield is formed so that at least the conductive shields on the top and bottom surfaces are electrically connected by a plating method. In addition, a semiconductor device can be formed at low cost with high productivity because a plating method is used for the formation of the conductive shield.Type: GrantFiled: November 3, 2011Date of Patent: April 16, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Yuugo Goto, Teruyuki Fujii
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Patent number: 8384601Abstract: An object of the present invention is to prevent electrical characteristics of circuit elements from being adversely affected by copper diffusion in a semiconductor device having an integrated circuit and an antenna formed over one substrate, which uses copper plating for the antenna. Another object is to prevent a defect of a semiconductor device due to poor connection between an antenna and an integrated circuit in a semiconductor device having the integrated circuit and the antenna formed over one substrate. In a semiconductor device having an integrated circuit 100 and an antenna 101 formed over one substrate 102, when a copper plating layer 108 is used for a conductor of the antenna 101, it is possible to decrease an adverse effect on electrical characteristics of circuit elements due to copper diffusion because a base layer 107 of the antenna 101 uses a nitride film of a predetermined metal.Type: GrantFiled: January 31, 2012Date of Patent: February 26, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Kazuya Hanaoka, Hideto Ohnuma, Teruyuki Fujii
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Patent number: 8313355Abstract: An object is to provide a semiconductor device with excellent reproducibility which is manufactured at low cost. A manufacturing method of a semiconductor device includes steps of forming a first electrode over a substrate; forming an insulating layer over the substrate and the first electrode; pressing a mold against the insulating layer to form an opening in the insulating layer; separating the mold from the insulating layer in which the opening is formed; hardening the insulating layer in which the opening is formed to form a partition wall; forming a light-emitting layer over the first electrode and the partition wall; and forming a second electrode over the light-emitting layer. The insulating layer contains a thermosetting resin material or a light curable resin material. The partition wall has a cross-sectional taper angle of 20 to 50°, and edges of a top and bottom thereof are rounded.Type: GrantFiled: June 5, 2007Date of Patent: November 20, 2012Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Teruyuki Fujii
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Publication number: 20120193435Abstract: An object of the present invention is to prevent electrical characteristics of circuit elements from being adversely affected by copper diffusion in a semiconductor device having an integrated circuit and an antenna formed over one substrate, which uses copper plating for the antenna. Another object is to prevent a defect of a semiconductor device due to poor connection between an antenna and an integrated circuit in a semiconductor device having the integrated circuit and the antenna formed over one substrate. In a semiconductor device having an integrated circuit 100 and an antenna 101 formed over one substrate 102, when a copper plating layer 108 is used for a conductor of the antenna 101, it is possible to decrease an adverse effect on electrical characteristics of circuit elements due to copper diffusion because a base layer 107 of the antenna 101 uses a nitride film of a predetermined metal.Type: ApplicationFiled: January 31, 2012Publication date: August 2, 2012Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Kazuya HANAOKA, Hideto Ohnuma, Teruyuki Fujii
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Publication number: 20120187396Abstract: A base insulating film is formed over a substrate. A first oxide semiconductor film is formed over the base insulating film, and then first heat treatment is performed to form a second oxide semiconductor film. Then, selective etching is performed to form a third oxide semiconductor film. An insulating film is formed over the first insulating film and the third oxide semiconductor film. A surface of the insulating film is polished to expose a surface of the third oxide semiconductor film, so that a sidewall insulating film is formed in contact with at least a side surface of the third oxide semiconductor film. Then, a source electrode and a drain electrode are formed over the sidewall insulating film and the third oxide semiconductor film. A gate insulating film and a gate electrode are formed.Type: ApplicationFiled: January 23, 2012Publication date: July 26, 2012Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Shunpei YAMAZAKI, Teruyuki FUJII, Sho NAGAMATSU
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Publication number: 20120146065Abstract: One pixel is divided into a first region including a first light emitting element and a second region including a second light emitting element, wherein the first region emits light in one direction and the second region emits light in the direction opposite to that of the first region. Independently driving the first light emitting element and the second light emitting element allows images to be displayed independently on the surface.Type: ApplicationFiled: December 22, 2011Publication date: June 14, 2012Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventors: Teruyuki Fujii, Shunpei Yamazaki