Patents by Inventor Teruyuki Fujii

Teruyuki Fujii has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120108014
    Abstract: An object is to provide a highly reliable semiconductor device that has tolerance to external stress and electrostatic discharge. Another object is to prevent defective shapes and defective characteristics due to the external stress or an electrostatic discharge in the manufacturing process, and to manufacture a semiconductor device with high yield. Still another object is to manufacture a semiconductor device at low cost and with high productivity. With the use of a conductive shield, electrostatic breakdown (malfunctions of the circuit or damages of a semiconductor element) due to electrostatic discharge of the semiconductor integrated circuit is prevented. The conductive shield is formed so that at least the conductive shields on the top and bottom surfaces are electrically connected by a plating method. In addition, a semiconductor device can be formed at low cost with high productivity because a plating method is used for the formation of the conductive shield.
    Type: Application
    Filed: November 3, 2011
    Publication date: May 3, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Yuugo GOTO, Teruyuki FUJII
  • Publication number: 20120074407
    Abstract: An object is to provide a semiconductor device having a novel structure in which a transistor including an oxide semiconductor and a transistor including a semiconductor material other than an oxide semiconductor are stacked. The semiconductor device includes a first transistor, an insulating layer over the first transistor, and a second transistor over the insulating layer. In the semiconductor device, the first transistor includes a first channel formation region, the second transistor includes a second channel formation region, the first channel formation region includes a semiconductor material different from a semiconductor material of the second channel formation region, and the insulating layer includes a surface whose root-mean-square surface roughness is less than or equal to 1 nm.
    Type: Application
    Filed: February 4, 2011
    Publication date: March 29, 2012
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei YAMAZAKI, Teruyuki FUJII, Ryota IMAHAYASHI, Shinya SASAGAWA, Motomu KURATA, Fumika TAGUCHI
  • Patent number: 8124544
    Abstract: It is an object of the present invention to provide a semiconductor device including a wiring having a preferable shape. A manufacturing method includes the steps of forming a first conductive layer connected to an element and a second conductive layer thereover; forming a resist mask over the second conductive layer; processing the second conductive layer by dry etching with the use of the mask; and processing the first conductive layer by wet etching with the mask left, wherein the etching rate of the second conductive layer is higher than that of the first conductive layer in the dry etching, and wherein the etching rate of the second conductive layer is the same as or more than that of the first conductive layer in the wet etching.
    Type: Grant
    Filed: June 3, 2009
    Date of Patent: February 28, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Satoru Okamoto, Teruyuki Fujii, Hideto Ohnuma, Akihiro Ishizuka
  • Patent number: 8111198
    Abstract: An object of the present invention is to prevent electrical characteristics of circuit elements from being adversely affected by copper diffusion in a semiconductor device having an integrated circuit and an antenna formed over the same substrate, which uses copper plating for the antenna. Another object is to prevent a defect of a semiconductor device due to poor connection between an antenna and an integrated circuit in a semiconductor device having the integrated circuit and the antenna formed over the same substrate. In a semiconductor device having an integrated circuit 100 and an antenna 101 formed over one substrate 102, when a copper plating layer 108 is used for a conductor of the antenna 101, it is possible to prevent copper diffusion to circuit elements and decrease an adverse effect on electrical characteristics of circuit elements due to the copper diffusion because a base layer 107 of the antenna 101 uses a nitride film of a predetermined metal.
    Type: Grant
    Filed: July 2, 2010
    Date of Patent: February 7, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kazuya Hanaoka, Hideto Ohnuma, Teruyuki Fujii
  • Patent number: 8084081
    Abstract: One pixel is divided into a first region including a first light emitting element and a second region including a second light emitting element, wherein the first region emits light in one direction and the second region emits light in the direction opposite to that of the first region. Independently driving the first light emitting element and the second light emitting element allows images to be displayed independently on the surface.
    Type: Grant
    Filed: April 2, 2007
    Date of Patent: December 27, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Teruyuki Fujii, Shunpei Yamazaki
  • Patent number: 8053253
    Abstract: An object is to provide a highly reliable semiconductor device that has tolerance to external stress and electrostatic discharge. Another object is to prevent defective shapes and defective characteristics due to the external stress or an electrostatic discharge in the manufacturing process, and to manufacture a semiconductor device with high yield. Still another object is to manufacture a semiconductor device at low cost and with high productivity. With the use of a conductive shield covering a semiconductor integrated circuit, electrostatic breakdown due to electrostatic discharge of the semiconductor integrated circuit is prevented. The conductive shield is formed so that at least the conductive shields on the top and bottom surfaces are electrically connected by a plating method. In addition, a semiconductor device can be formed at low cost with high productivity because a plating method is used for the formation of the conductive shield.
    Type: Grant
    Filed: May 28, 2009
    Date of Patent: November 8, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yuugo Goto, Teruyuki Fujii
  • Publication number: 20110220891
    Abstract: A semiconductor device includes a wiring embedded in an insulating layer, an oxide semiconductor layer over the insulating layer, a source electrode and a drain electrode electrically connected to the oxide semiconductor layer, a gate electrode provided to overlap with the oxide semiconductor layer, and a gate insulating layer provided between the oxide semiconductor layer and the gate electrode. The insulating layer is formed so that part of a top surface of the wiring is exposed. The part of the top surface of the wiring is positioned higher than part of a surface of the insulating layer. The wiring in a region exposed from the insulating layer is electrically connected to the source electrode or the drain electrode. The root-mean-square roughness of a region which is part of the surface of the insulating layer and in contact with the oxide semiconductor layer is 1 nm or less.
    Type: Application
    Filed: March 3, 2011
    Publication date: September 15, 2011
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Teruyuki FUJII, Ryota IMAHAYASHI
  • Patent number: 7969363
    Abstract: An object of the present invention is to prevent electrical characteristics of circuit elements from being adversely affected by copper diffusion in a semiconductor device having an integrated circuit and an antenna formed over the same substrate, which uses copper plating for the antenna. Another object is to prevent a defect of a semiconductor device due to poor connection between an antenna and an integrated circuit in a semiconductor device having the integrated circuit and the antenna formed over the same substrate. In a semiconductor device having an integrated circuit 100 and an antenna 101 formed over one substrate 102, when a copper plating layer 108 is used for a conductor of the antenna 101, it is possible to prevent copper diffusion to circuit elements and decrease an adverse effect on electrical characteristics of circuit elements due to the copper diffusion because a base layer 107 of the antenna 101 uses a nitride film of a predetermined metal.
    Type: Grant
    Filed: July 2, 2010
    Date of Patent: June 28, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kazuya Hanaoka, Hideto Ohnuma, Teruyuki Fujii
  • Publication number: 20100275989
    Abstract: An object relates to an electrode of a semiconductor device or a method for manufacturing a semiconductor device, which includes a bonding step, and problems are: (1) high resistance of a semiconductor device due to the use of an Al electrode, (2) formation of an alloy by Al and Si, (3) high resistance of a film formed by a sputtering method, and (4) defective bonding in a bonding step which is caused if a bonding surface has a large unevenness. A semiconductor device includes a metal substrate or a substrate provided with a metal film, a copper (Cu) plating film over and bonded to the metal substrate or the metal film by employing a thermocompression bonding method, a barrier film over the Cu plating film, a single crystal silicon film over the barrier film, and an electrode layer over the single crystal silicon film.
    Type: Application
    Filed: April 23, 2010
    Publication date: November 4, 2010
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Teruyuki FUJII, Kohei OHSHIMA, Junya MARUYAMA, Akihisa SHIMOMURA
  • Publication number: 20100270868
    Abstract: An object of the present invention is to prevent electrical characteristics of circuit elements from being adversely affected by copper diffusion in a semiconductor device having an integrated circuit and an antenna formed over the same substrate, which uses copper plating for the antenna. Another object is to prevent a defect of a semiconductor device due to poor connection between an antenna and an integrated circuit in a semiconductor device having the integrated circuit and the antenna formed over the same substrate. In a semiconductor device having an integrated circuit 100 and an antenna 101 formed over one substrate 102, when a copper plating layer 108 is used for a conductor of the antenna 101, it is possible to prevent copper diffusion to circuit elements and decrease an adverse effect on electrical characteristics of circuit elements due to the copper diffusion because a base layer 107 of the antenna 101 uses a nitride film of a predetermined metal.
    Type: Application
    Filed: July 2, 2010
    Publication date: October 28, 2010
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Kazuya Hanaoka, Hideto Ohnuma, Teruyuki Fujii
  • Patent number: 7750852
    Abstract: An object of the present invention is to prevent electrical characteristics of circuit elements from being adversely affected by copper diffusion in a semiconductor device having an integrated circuit and an antenna formed over the same substrate, which uses copper plating for the antenna. Another object is to prevent a defect of a semiconductor device due to poor connection between an antenna and an integrated circuit in a semiconductor device having the integrated circuit and the antenna formed over the same substrate. In a semiconductor device having an integrated circuit 100 and an antenna 101 formed over one substrate 102, when a copper plating layer 108 is used for a conductor of the antenna 101, it is possible to prevent copper diffusion to circuit elements and decrease an adverse effect on electrical characteristics of circuit elements due to the copper diffusion because a base layer 107 of the antenna 101 uses a nitride film of a predetermined metal.
    Type: Grant
    Filed: March 26, 2008
    Date of Patent: July 6, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kazuya Hanaoka, Hideto Ohnuma, Teruyuki Fujii
  • Publication number: 20090305467
    Abstract: An object is to provide a highly reliable semiconductor device that is reduced in thickness and size and has tolerance to external stress and electrostatic discharge. Another object is to prevent defective shapes and defective characteristics due to the external stress or an electrostatic discharge in the manufacturing process, and to manufacture a semiconductor device with high yield. Still another object is to manufacture a semiconductor device at low cost and with high productivity. With the use of a conductive shield covering a semiconductor integrated circuit, electrostatic breakdown (malfunctions of the circuit or damages of a semiconductor element) due to electrostatic discharge of the semiconductor integrated circuit is prevented. The conductive shield is formed so that at least the conductive shields on the top and bottom surfaces are electrically connected by a plating method.
    Type: Application
    Filed: May 28, 2009
    Publication date: December 10, 2009
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Yuugo GOTO, Teruyuki FUJII
  • Publication number: 20090246953
    Abstract: It is an object of the present invention to provide a semiconductor device including a wiring having a preferable shape. A manufacturing method includes the steps of forming a first conductive layer connected to an element and a second conductive layer thereover; forming a resist mask over the second conductive layer; processing the second conductive layer by dry etching with the use of the mask; and processing the first conductive layer by wet etching with the mask left, wherein the etching rate of the second conductive layer is higher than that of the first conductive layer in the dry etching, and wherein the etching rate of the second conductive layer is the same as or more than that of the first conductive layer in the wet etching.
    Type: Application
    Filed: June 3, 2009
    Publication date: October 1, 2009
    Inventors: Satoru Okamoto, Teruyuki Fujii, Hideto Ohnuma, Akihiro Ishizuka
  • Patent number: 7547627
    Abstract: It is an object of the present invention to provide a semiconductor device including a wiring having a preferable shape. A manufacturing method includes the steps of forming a first conductive layer connected to an element and a second conductive layer thereover; forming a resist mask over the second conductive layer; processing the second conductive layer by dry etching with the use of the mask; and processing the first conductive layer by wet etching with the mask left, wherein the etching rate of the second conductive layer is higher than that of the first conductive layer in the dry etching, and wherein the etching rate of the second conductive layer is the same as or more than that of the first conductive layer in the wet etching.
    Type: Grant
    Filed: November 15, 2005
    Date of Patent: June 16, 2009
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Satoru Okamoto, Teruyuki Fujii, Hideto Ohnuma, Akihiro Ishizuka
  • Patent number: 7470621
    Abstract: It is an object of the present invention to provide a method for manufacturing a semiconductor device that can suppress generation of a crack and peeling in a resin BM and deterioration of coverage of an upper layer of the resin BM, even if a black resin is used as a material of the resin BM in order to improve a contrast of brightness and a contrast of color.
    Type: Grant
    Filed: July 6, 2006
    Date of Patent: December 30, 2008
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Taichi Endo, Teruyuki Fujii, Kiyofumi Ogino
  • Publication number: 20080309581
    Abstract: In a semiconductor device in which a copper plating layer is used for a conductor of an antenna and in which an integrated circuit and the antenna are formed over the same substrate, an object is to prevent an adverse effect on electrical characteristics of a circuit element due to diffusion of copper, as well as to provide a copper plating layer with favorable adhesiveness. Another object is to prevent a defect in the semiconductor device that stems from poor connection between the antenna and the integrated circuit, in the semiconductor device in which the integrated circuit and the antenna are formed over the same substrate. In the semiconductor device, a copper plating layer is used for the antenna, an alloy of Ag, Pd, and Cu is used for a seed layer thereof, and TiN or Ti is used for a barrier layer.
    Type: Application
    Filed: June 9, 2008
    Publication date: December 18, 2008
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Teruyuki Fujii, Kazuya Hanaoka
  • Publication number: 20080252531
    Abstract: An object of the present invention is to prevent electrical characteristics of circuit elements from being adversely affected by copper diffusion in a semiconductor device having an integrated circuit and an antenna formed over the same substrate, which uses copper plating for the antenna. Another object is to prevent a defect of a semiconductor device due to poor connection between an antenna and an integrated circuit in a semiconductor device having the integrated circuit and the antenna formed over the same substrate. In a semiconductor device having an integrated circuit 100 and an antenna 101 formed over one substrate 102, when a copper plating layer 108 is used for a conductor of the antenna 101, it is possible to prevent copper diffusion to circuit elements and decrease an adverse effect on electrical characteristics of circuit elements due to the copper diffusion because a base layer 107 of the antenna 101 uses a nitride film of a predetermined metal.
    Type: Application
    Filed: March 26, 2008
    Publication date: October 16, 2008
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Kazuya HANAOKA, Hideto OHNUMA, Teruyuki FUJII
  • Publication number: 20080206997
    Abstract: A method for manufacturing an insulating film, by which the insulating film can be formed of a non-photosensitive siloxane resin and formed into a desired shape by wet etching. A thin film is formed with a suspension in which a siloxane resin or a siloxane-based material is included in an organic solvent; a first heat treatment is performed on the thin film; a mask is formed over the thin film after the first heat treatment; wet etching with an organic solvent is performed to process the shape of the thin film after the first heat treatment; and a second heat treatment is performed on the processed thin film.
    Type: Application
    Filed: February 11, 2008
    Publication date: August 28, 2008
    Inventor: Teruyuki Fujii
  • Publication number: 20070292986
    Abstract: An object is to provide a semiconductor device with excellent reproducibility which is manufactured at low cost. A method for manufacturing a semiconductor device includes steps of forming a first electrode over a substrate; forming an insulating layer over the substrate and the first electrode; pressing a mold against the insulating layer to form an opening in the insulating layer; separating the mold from the insulating layer in which opening is formed; hardening the insulating layer in which the opening is formed to form a partition wall; forming a light-emitting layer over the first electrode and the partition wall; and forming a second electrode over the light-emitting layer. As a method for forming the partition wall, nano-imprinting is used. An insulating layer contains polysilane. The partition wall formed of a silicon oxide film is formed by UV light irradiation and heating.
    Type: Application
    Filed: June 4, 2007
    Publication date: December 20, 2007
    Inventor: Teruyuki Fujii
  • Publication number: 20070287209
    Abstract: To obtain a long-life light-emitting device. The invention relates to a manufacturing method of a light-emitting device, including forming a first electrode over a substrate, forming a partition wall using a resin material over the substrate and the first electrode, holding the partition wall for a first time period by hour at a first temperature which is lower than the curing temperature, holding the partition wall for a second time period by hour at a second temperature which is higher than the curing temperature after holding at the first temperature, forming a light-emitting layer over the partition wall so as to be in contact with the first electrode after holding at the second temperature, and forming a second electrode over the light-emitting layer. Accordingly, moisture or gas generation from a partition wall can be suppressed, and a life of a light-emitting element can be prolonged.
    Type: Application
    Filed: April 19, 2007
    Publication date: December 13, 2007
    Inventor: Teruyuki Fujii