Abstract: A semiconductor memory device includes: a semiconductor substrate; a memory cell array disposed separately from the semiconductor substrate in a first direction; and first and second transistor arrays disposed on the semiconductor substrate. The semiconductor substrate includes a first region to a fourth region arranged in a second direction and a fifth region to an eighth region arranged in the second direction. These regions are each adjacent in a third direction. The memory cell array includes first conducting layers disposed in the first to fourth regions and second conducting layers disposed in the fifth to eighth regions. The first transistor array includes transistors connected to the plurality of first conducting layers via contacts disposed in the second region. The second transistor array includes transistors connected to the plurality of second conducting layers via contacts disposed in the seventh region.

Abstract: A semiconductor memory device includes a semiconductor substrate, transistors formed in an upper surface of the semiconductor substrate, a stacked body provided on the semiconductor substrate, a first contact, and a second contact. The transistors are arranged along a first direction. A minimum period of an arrangement of the transistors is a first period. The stacked body includes electrode films. A configuration of a first portion of the stacked body is a staircase-like having terraces. A first region and a second region are set along the first direction in the first portion. A length in the first direction of the terrace disposed in the second region is longer than the first period. A length in the first direction of the terrace disposed in the first region is shorter than the first period.

Abstract: A semiconductor storage device includes a first input driver configured to receive a first signal from a memory controller, a second input driver configured to receive a chip enable signal from the memory controller, and a first control circuit. The first control circuit is configured to set the semiconductor storage device in an enabled state or a disabled state depending on whether or not the first signal which is received during a time period that starts with assertion of the chip enable signal and is prior to receipt of a command sequence, corresponds to a first chip address.

Abstract: A semiconductor storage device includes a first input driver configured to receive a first signal from a memory controller, a second input driver configured to receive a chip enable signal from the memory controller, and a first control circuit. The first control circuit is configured to set the semiconductor storage device in an enabled state or a disabled state depending on whether or not the first signal which is received during a time period that starts with assertion of the chip enable signal and is prior to receipt of a command sequence, corresponds to a first chip address.

Abstract: A semiconductor memory device includes: a semiconductor substrate; a memory cell array disposed separately from the semiconductor substrate in a first direction; and first and second transistor arrays disposed on the semiconductor substrate. The semiconductor substrate includes a first region to a fourth region arranged in a second direction and a fifth region to an eighth region arranged in the second direction. These regions are each adjacent in a third direction. The memory cell array includes first conducting layers disposed in the first to fourth regions and second conducting layers disposed in the fifth to eighth regions. The first transistor array includes transistors connected to the plurality of first conducting layers via contacts disposed in the second region. The second transistor array includes transistors connected to the plurality of second conducting layers via contacts disposed in the seventh region.

Abstract: A semiconductor storage device includes a first conductive layer, a second conductive layer, a third conductive layer, a contact plug, a memory trench extending between the second conductive layer and the third conductive layer. The memory trench is formed around the contact plug, and surrounds a first area in which the contact plug is disposed. A second area is separated from the first area and includes a pillar penetrating the first conductive layer. The second conductive layer extends between the first and second areas, and is connected to the first conductive layer. The third conductive layer is on the opposite side of the first area to the second area, and is connected to the first conductive layer.

Abstract: A semiconductor memory device includes a semiconductor substrate, transistors formed in an upper surface of the semiconductor substrate, a stacked body provided on the semiconductor substrate, a first contact, and a second contact. The transistors are arranged along a first direction. A minimum period of an arrangement of the transistors is a first period. The stacked body includes electrode films. A configuration of a first portion of the stacked body is a staircase-like having terraces. A first region and a second region are set along the first direction in the first portion. A length in the first direction of the terrace disposed in the second region is longer than the first period. A length in the first direction of the terrace disposed in the first region is shorter than the first period.

Abstract: A semiconductor device includes a substrate and a first semiconductor layer and a second semiconductor layer each extending in a first direction perpendicular to a surface of the substrate. Furthermore, the semiconductor device includes a first plug provided on the first semiconductor layer and a second plug provided on the second semiconductor layers, and a connection wiring having an upper surface that is at a same height along the first direction as upper surfaces of the first and second plugs, and having a lower surface that is at a same height along the first direction as lower surfaces of the first and second plugs. Furthermore, the semiconductor device includes a first wiring provided on the first plug and the connection wiring and a second wiring provided on the second plug and the connection wiring.

Abstract: A semiconductor memory device includes: a semiconductor substrate; a memory cell array disposed separately from the semiconductor substrate in a first direction; and first and second transistor arrays disposed on the semiconductor substrate. The semiconductor substrate includes a first region to a fourth region arranged in a second direction and a fifth region to an eighth region arranged in the second direction. These regions are each adjacent in a third direction. The memory cell array includes first conducting layers disposed in the first to fourth regions and second conducting layers disposed in the fifth to eighth regions. The first transistor array includes transistors connected to the plurality of first conducting layers via contacts disposed in the second region. The second transistor array includes transistors connected to the plurality of second conducting layers via contacts disposed in the seventh region.

Abstract: A semiconductor storage device includes first and second chips and first and second power supply electrodes. The first chip includes conductive layers arranged in a first direction, a semiconductor pillar extending in the first direction and facing the conductive layers, first contacts extending in the first direction and connected to the conductive layers, second contacts extending in the first direction and connected to a first power supply electrode, third contacts extending in the first direction, facing the second contacts in a direction crossing the first direction, and connected to the second power supply electrode, and first bonding electrodes connected to the first contacts. The second chip includes a semiconductor substrate, transistors provided on the semiconductor substrate, fourth contacts connected to the transistors, and second bonding electrodes connected to the fourth contacts.

Abstract: According to one embodiment, a semiconductor memory device includes a memory cell, a first voltage generator and a second voltage generator. The memory cell is provided above a substrate. The first voltage generator is provided between the substrate and the memory cell. The first voltage generator is configured to generate a first voltage to be supplied to the memory cell. The second voltage generator is provided between the substrate and the memory cell. The second voltage generator is configured to generate the first voltage and have a circuit configuration equivalent to the first voltage generator.

Abstract: A semiconductor memory device includes a memory chip. The memory chip includes a first region including a plurality of first memory cells and second memory cells, a second region different from the first region, a plurality of first word lines stacked apart from each other in a first direction in the first and second regions, a first pillar including a first semiconductor layer extending through the first word lines, and a first insulator layer provided between the first semiconductor layer and the first word lines, in the first region, the first memory cells being located at intersections of the first pillar with the first word lines, a first bonding pad in the second region, and a first transistor between the first word lines and the first bonding pad, and connected between one of the first word lines and the first bonding pad, in the second region.

Abstract: A semiconductor device includes: a semiconductor substrate; a plurality of transistors provided on a surface of the semiconductor substrate; and a first circuit electrically connected to gate electrodes of the plurality of transistors. The plurality of transistors include: a first transistor and a second transistor that are adjacent via an insulating region in a first direction; a third transistor that is adjacent to the first transistor and the second transistor via the insulating region in a second direction intersecting the first direction; and a fourth transistor that is adjacent to the first transistor and the second transistor via the insulating region in the second direction. The first circuit sets the first through fourth transistors to an ON state according to a first signal.

Abstract: A semiconductor storage device includes a first conductive layer, a second conductive layer, a third conductive layer, a contact plug, a memory trench extending between the second conductive layer and the third conductive layer. The memory trench is formed around the contact plug, and surrounds a first area in which the contact plug is disposed. A second area is separated from the first area and includes a pillar penetrating the first conductive layer. The second conductive layer extends between the first and second areas, and is connected to the first conductive layer. The third conductive layer is on the opposite side of the first area to the second area, and is connected to the first conductive layer.

Abstract: A semiconductor memory device includes a semiconductor substrate, transistors formed in an upper surface of the semiconductor substrate, a stacked body provided on the semiconductor substrate, a first contact, and a second contact. The transistors are arranged along a first direction. A minimum period of an arrangement of the transistors is a first period. The stacked body includes electrode films. A configuration of a first portion of the stacked body is a staircase-like having terraces. A first region and a second region are set along the first direction in the first portion. A length in the first direction of the terrace disposed in the second region is longer than the first period. A length in the first direction of the terrace disposed in the first region is shorter than the first period.

Abstract: A semiconductor memory device includes a semiconductor substrate, transistors formed in an upper surface of the semiconductor substrate, a stacked body provided on the semiconductor substrate, a first contact, and a second contact. The transistors are arranged along a first direction. A minimum period of an arrangement of the transistors is a first period. The stacked body includes electrode films. A configuration of a first portion of the stacked body is a staircase-like having terraces. A first region and a second region are set along the first direction in the first portion. A length in the first direction of the terrace disposed in the second region is longer than the first period. A length in the first direction of the terrace disposed in the first region is shorter than the first period.

Abstract: A semiconductor device includes: a semiconductor substrate; a plurality of transistors provided on a surface of the semiconductor substrate; and a first circuit electrically connected to gate electrodes of the plurality of transistors. The plurality of transistors include: a first transistor and a second transistor that are adjacent via an insulating region in a first direction; a third transistor that is adjacent to the first transistor and the second transistor via the insulating region in a second direction intersecting the first direction; and a fourth transistor that is adjacent to the first transistor and the second transistor via the insulating region in the second direction. The first circuit sets the first through fourth transistors to an ON state according to a first signal.

Abstract: A semiconductor memory device includes a semiconductor substrate, transistors formed in an upper surface of the semiconductor substrate, a stacked body provided on the semiconductor substrate, a first contact, and a second contact. The transistors are arranged along a first direction. A minimum period of an arrangement of the transistors is a first period. The stacked body includes electrode films. A configuration of a first portion of the stacked body is a staircase-like having terraces. A first region and a second region are set along the first direction in the first portion. A length in the first direction of the terrace disposed in the second region is longer than the first period. A length in the first direction of the terrace disposed in the first region is shorter than the first period.

Abstract: A semiconductor memory device includes a semiconductor substrate, transistors formed in an upper surface of the semiconductor substrate, a stacked body provided on the semiconductor substrate, a first contact, and a second contact. The transistors are arranged along a first direction. A minimum period of an arrangement of the transistors is a first period. The stacked body includes electrode films. A configuration of a first portion of the stacked body is a staircase-like having terraces. A first region and a second region are set along the first direction in the first portion. A length in the first direction of the terrace disposed in the second region is longer than the first period. A length in the first direction of the terrace disposed in the first region is shorter than the first period.

Abstract: A semiconductor memory device includes a plurality of word lines stacked in a first direction; a semiconductor pillar extending through the plurality of word lines in the first direction; a source line electrically connected to the semiconductor pillar; and a transistor arranged in the first direction with the plurality of word lines. The transistor includes a gate electrode, source and drain regions positioned on both sides of the gate electrode respectively. The source line is positioned between the transistor and the plurality of word lines, and is electrically connected to one of the source and drain regions.