Abstract: A semiconductor memory device includes first wires extending in a first direction; second wires provided in a first interconnect layer including the first wires, the second wires extending in the first direction along extension lines of the first wires respectively; third wires provided in a second interconnect layer different from the first interconnect layer; and transistors on/off controlling electrical connections between the first wires and the second wires through the third wires. The first and second wires are arranged respectively in a second direction crossing the first direction. The transistors are disposed in M stages (M is integer not less than 2) in the first direction, the M stages each including a transistor array aligned in the second direction. The first second wires are periodically arranged with the minimum period including M times N first wires (N is integer not less than 2) and M times N second wires.

Abstract: A semiconductor memory device includes first wires extending in a first direction; second wires provided in a first interconnect layer including the first wires, the second wires extending in the first direction along extension lines of the first wires respectively; third wires provided in a second interconnect layer different from the first interconnect layer; and transistors on/off controlling electrical connections between the first wires and the second wires through the third wires. The first and second wires are arranged respectively in a second direction crossing the first direction. The transistors are disposed in M stages (M is integer not less than 2) in the first direction, the M stages each including a transistor array aligned in the second direction. The first second wires are periodically arranged with the minimum period including M times N first wires (N is integer not less than 2) and M times N second wires.

Abstract: A semiconductor memory device includes a semiconductor substrate, transistors formed in an upper surface of the semiconductor substrate, a stacked body provided on the semiconductor substrate, a first contact, and a second contact. The transistors are arranged along a first direction. A minimum period of an arrangement of the transistors is a first period. The stacked body includes electrode films. A configuration of a first portion of the stacked body is a staircase-like having terraces. A first region and a second region are set along the first direction in the first portion. A length in the first direction of the terrace disposed in the second region is longer than the first period. A length in the first direction of the terrace disposed in the first region is shorter than the first period.

Abstract: A semiconductor memory device includes a plurality of word lines stacked in a first direction; a semiconductor pillar extending through the plurality of word lines in the first direction; a source line electrically connected to the semiconductor pillar; and a transistor arranged in the first direction with the plurality of word lines. The transistor includes a gate electrode, source and drain regions positioned on both sides of the gate electrode respectively. The source line is positioned between the transistor and the plurality of word lines, and is electrically connected to one of the source and drain regions.

Abstract: A device includes first and second semiconductor-regions located in a substrate which are adjacent to each other at a boundary. First contacts are located in the first semiconductor-region along the boundary and are electrically connected to the first semiconductor-region. Second contacts are located in the second semiconductor-region along the boundary and are electrically connected to the second semiconductor-region. The second contacts are not located in parts of the second semiconductor-region on an opposite side to the first contacts across the boundary. The parts of the second semiconductor-region are adjacent to the first contacts in a first direction s perpendicular to an arranging direction of the first and second contacts. The first contacts are not located in parts of the first semiconductor-region on an opposite side to the second contacts across the boundary. The parts of the first semiconductor-region are adjacent to second contacts in the first direction.

Abstract: A device includes first and second semiconductor-regions located in a substrate which are adjacent to each other at a boundary. First contacts are located in the first semiconductor-region along the boundary and are electrically connected to the first semiconductor-region. Second contacts are located in the second semiconductor-region along the boundary and are electrically connected to the second semiconductor-region. The second contacts are not located in parts of the second semiconductor-region on an opposite side to the first contacts across the boundary. The parts of the second semiconductor-region are adjacent to the first contacts in a first direction s perpendicular to an arranging direction of the first and second contacts. The first contacts are not located in parts of the first semiconductor-region on an opposite side to the second contacts across the boundary. The parts of the first semiconductor-region are adjacent to second contacts in the first direction.

Abstract: In one embodiment, a semiconductor integrated circuit includes power supply strap wires extending in a first direction in a first layer, auxiliary power supply strap wires extending in the first direction in a second layer below the first layer, and intermediate power supply wires each electrically connecting one of the power supply strap wires to one of the auxiliary power supply strap wires in a third layer between the first and second layers. The circuit further includes power supply rails extending in a second direction in a fourth layer below the second layer, and upper power supply strap wires extending in the second direction in a fifth layer above the first layer. An interval between the intermediate power supply wires is larger than an interval between the power supply rails, and is smaller than an interval between the upper power supply strap wires.

Abstract: A D-type flip-flop according to embodiments comprises: a transmission element configured in a slave latch, the transmission element fetching an output of a first latch circuit and outputting the fetched output to a first node, based on a clock signal; a first latch circuit constituting element configured in the first latch circuit, the first latch circuit giving an output of one logical value to the first node through the transmission element with the output fixed in a second mode; and a second latch circuit constituting element configured in the second latch circuit that holds a signal which appears at the first node, the second latch circuit constituting element giving an output of other logical value to the first node based on the clock signal with the output fixed in the second mode.

Abstract: The verification apparatus for a semiconductor integrated circuit verifies a logic equivalence before and after modification to the circuit by replacing a memory with a divisional memory model that agrees with the memory in number of input and output pins and verifying logics at an input and an output thereof.

Abstract: The verification apparatus for a semiconductor integrated circuit verifies a logic equivalence before and after modification to the circuit by replacing a memory with a divisional memory model that agrees with the memory in number of input and output pins and verifying logics at an input and an output thereof.

Abstract: In one embodiment, a semiconductor integrated circuit includes power supply strap wires extending in a first direction in a first layer, auxiliary power supply strap wires extending in the first direction in a second layer below the first layer, and intermediate power supply wires each electrically connecting one of the power supply strap wires to one of the auxiliary power supply strap wires in a third layer between the first and second layers. The circuit further includes power supply rails extending in a second direction in a fourth layer below the second layer, and upper power supply strap wires extending in the second direction in a fifth layer above the first layer. An interval between the intermediate power supply wires is larger than an interval between the power supply rails, and is smaller than an interval between the upper power supply strap wires.

Abstract: According to an embodiment, a semiconductor integrated circuit including first and second lower-layer power supply wires extending in a first direction and first and second upper-layer power supply wires extending in a second direction is provided. First and second connection wires between the upper-layer power supply wires and the lower-layer power supply wires are arranged in a same line along the second direction. First and second position converting wires extending from the connection wires are arranged between the first and second connection wires. First and second upper-side vias provided on the position converting wires are arranged in a same line along the first direction.

Abstract: A wiring method for a semiconductor integrated circuit has the steps of, separately from a first layer on which a first signal wiring pattern is mainly formed, laying out a first power-supply wiring pattern on a second layer so that a plurality of rows of the first power-supply wiring pattern are regularly arranged with vacant areas each interposed between the rows and making narrower a width of each vacant area than a narrowest width of a row among the rows of the first power-supply wiring pattern, and laying out a second signal wiring pattern electrically conductive to the first layer in two or more rows of the vacant areas on the second layer so that the second signal wiring pattern is not in contact with adjacent rows of the first power-supply wiring pattern on both sides.

Abstract: According to one embodiment, a designing apparatus includes a register position determining module, a net list generator, and a layout data generator. The register position determining module determines a register position on a layout of a semiconductor integrated circuit from a hardware description. The net list generator generates a net list according to the register position. The layout data generator generates layout data based on the net list. The layout data indicates the layout of the semiconductor integrated circuit.

Abstract: According to one embodiment, a designing apparatus includes a register position determining module, a net list generator, and a layout data generator. The register position determining module determines a register position on a layout of a semiconductor integrated circuit from a hardware description. The net list generator generates a net list according to the register position. The layout data generator generates layout data based on the net list. The layout data indicates the layout of the semiconductor integrated circuit.

Abstract: According to an embodiment, a semiconductor integrated circuit including first and second lower-layer power supply wires extending in a first direction and first and second upper-layer power supply wires extending in a second direction is provided. First and second connection wires between the upper-layer power supply wires and the lower-layer power supply wires are arranged in a same line along the second direction. First and second position converting wires extending from the connection wires are arranged between the first and second connection wires. First and second upper-side vias provided on the position converting wires are arranged in a same line along the first direction.

Abstract: A wiring method for a semiconductor integrated circuit has the steps of, separately from a first layer on which a first signal wiring pattern is mainly formed, laying out a first power-supply wiring pattern on a second layer so that a plurality of rows of the first power-supply wiring pattern are regularly arranged with vacant areas each interposed between the rows and making narrower a width of each vacant area than a narrowest width of a row among the rows of the first power-supply wiring pattern, laying out a second signal wiring pattern electrically conductive to the first layer in two or more rows of the vacant areas on the second layer so that the second signal wiring pattern is not in contact with adjacent rows of the first power-supply wiring pattern on both sides, and laying out a second power-supply wiring pattern further in at least a portion of a pattern-layout allowable area remaining in the vacant areas.

Abstract: This disclosure concerns a semiconductor circuit design method for designing a clock wiring structure supplying a clock to a flip-flop by using a computer. The semiconductor circuit design method comprises setting the flip-flop based on circuit information on a semiconductor integrated circuit; obtaining a control signal controlling the flip-flop; calculating a first evaluation value indicating a power consumption and a magnitude of a clock skew time when clock gating is applied to the flip-flop; setting a gated clock structure clock-gating the flip-flop when the first evaluation value is higher than a first threshold; calculating a second evaluation value indicating the power consumption and a magnitude of a cell area when a low power flip-flop lower in power consumption than the flip-flop is applied to the flip-flop; and replacing the flip-flop by the lower power flip-flop when the second evaluation value is higher than a second threshold.

Abstract: A semiconductor layout design apparatus has an inter-block connection information extracting part, a cell initial placement part and an evaluation value. The inter-block connection information extracting part configured to extract the number of wiring connections between a plurality of blocks including standard cells and macrocells based on a net list, library information, floor plan information and technology information. The cell initial placement part configured to initially place the standard cells and the macrocells in an placement region to generate an initial floor plan. The evaluation value calculating part configured to calculate an evaluation value of the floor plan based on distances between a plurality of blocks including the standard cells and the macrocells initially placed by the cell initial placement part and the extracted number of the wiring connections between a plurality of blocks.

Abstract: A semiconductor layout design apparatus has an inter-block connection information extracting part, a block global placement part and a cell placement setting part. The inter-block connection information extracting part configured to extract the number of wiring connections between a plurality of blocks including standard cells and macrocells based on a net list, library information, floor plan information and technology information. The block global placement part configured to roughly place the plurality of blocks in a placement region on a semiconductor substrate. The cell placement setting part configured to set placement positions of the macrocells in the block based on a positioning relationship with the other block and the number of the wiring connections with the other block with respect to each of the plurality of blocks roughly placed by the block global placement part.