Patents by Inventor Tetsuhiro Iwai
Tetsuhiro Iwai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20040050496Abstract: In a plasma processing apparatus for plasma-processing a silicon wafer 6 to which a protective film 6a is stuck in a state that the silicon wafer 6 is held by a first electrode 3 by electrostatic absorption and is being cooled, the top surface 3g of the first electrode 3 consists of a top surface central area A that is inside a boundary line P2 that is distant inward by a prescribed length from the outer periphery P1 of the silicon wafer 6 and in which the conductor is exposed, and a ring-shaped top surface peripheral area B that surrounds the top surface central area A and in which the conductor is covered with an insulating coating 3f. This structure makes it possible to hold the silicon wafer 6 by sufficient electrostatic holding force by bringing the silicon wafer 6 into direct contact with the conductor and to increase the cooling efficiency by virtue of heat conduction from the silicon wafer 6 to the first electrode 3.Type: ApplicationFiled: July 17, 2003Publication date: March 18, 2004Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Tetsuhiro Iwai, Kiyoshi Arita
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Publication number: 20030082914Abstract: A semiconductor wafer processing apparatus grinds a surface of a semiconductor wafer by mechanical grinding, and then removes a damaged layer in the ground surface. In the processing apparatus, a grinding portion, a precenter portion, a wafer cleaning portion, plasma treatment portions, and magazines are arranged radially about an origin of a polar coordinate system of a third wafer transport portion having a robot mechanism, and their positions of arrangement are set such that the origin is located on lines of extension of wafer carry-in and carry-out center lines of the plasma treatment portions. Thus, the number of changed grippings of the semiconductor wafer can be minimized to prevent breakage of the semiconductor wafer. Moreover, transfer of the semiconductor wafer between the respective portions can be covered by the single robot mechanism, and the equipment can be made compact.Type: ApplicationFiled: December 11, 2002Publication date: May 1, 2003Inventors: Yutaka Koma, Kiyoshi Arita, Hiroshi Haji, Tetsuhiro Iwai
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Patent number: 6551444Abstract: A plasma processing apparatus and a method of plasma processing using the same obviate a problem in which an excessive amount of processing gas is supplied momentarily during an initial stage of the gas supply. In the process of supplying gas, a main controller outputs to a mass flow controller a flow-rate setting command signal preset for “zero flow” prior to opening a gas shut-off valve, which opens/closes a gas supply passage, and another flow-rate setting command signal set for “a specific flow rate” only after the gas shut-off valve is opened.Type: GrantFiled: April 9, 2002Date of Patent: April 22, 2003Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Tetsuhiro Iwai, Ryota Furukawa
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Publication number: 20030037882Abstract: In a plasma treating apparatus for carrying out a plasma treatment over a silicon wafer 6 having a protective tape 6a stuck to a circuit formation face, the silicon wafer 6 is mounted on a mounting surface 3d which is provided on an upper surface of a lower electrode 3 formed of a conductive metal with the protective tape 6a turned toward the mounting surface 3d. When a DC voltage is to be applied to the lower electrode 3 by a DC power portion 18 for electrostatic adsorption to adsorb and hold the silicon wafer 6 onto the lower electrode 3 in the plasma treatment, the protective tape 6a is utilized as a dielectric for the electrostatic adsorption. Consequently, the dielectric can be thinned as much as possible and the silicon wafer 6 can be held by a sufficient electrostatic holding force.Type: ApplicationFiled: August 26, 2002Publication date: February 27, 2003Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Kiyoshi Arita, Tetsuhiro Iwai, Junichi Terayama
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Patent number: 6511895Abstract: A semiconductor wafer processing apparatus grinds a surface of a semiconductor wafer by mechanical grinding, and then removes a damaged layer in the ground surface. In the processing apparatus, a grinding portion, a precenter portion, a wafer cleaning portion, plasma treatment portions, and magazines are arranged radially about an origin of a polar coordinate system of a third wafer transport portion having a robot mechanism, and their positions of arrangement are set such that the origin is located on lines of extension of wafer carry-in and carry-out center lines of the plasma treatment portions. Thus, the number of changed grippings of the semiconductor wafer can be minimized to prevent breakage of the semiconductor wafer. Moreover, transfer of the semiconductor wafer between the respective portions can be covered by the single robot mechanism, and the equipment can be made compact.Type: GrantFiled: February 26, 2001Date of Patent: January 28, 2003Assignees: Disco Corporation, Matsushita Electric Industrial Co., Ltd.Inventors: Yutaka Koma, Kiyoshi Arita, Hiroshi Haji, Tetsuhiro Iwai
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Electrode member for plasma treating apparatus, plasma treating apparatus and plasma treating method
Publication number: 20020195202Abstract: In a plasma treating apparatus, a ceramic porous substance having a three-dimensional network structure in which a frame portion formed of ceramic containing alumina is provided continuously like a three-dimensional network is used for the material of an electrode member for the plasma treating apparatus to be attached to the front surface of a gas supplying port of an electrode for plasma generation, and a gas for plasma generation is caused to pass through a hole portion formed irregularly in the three-dimensional network structure. Consequently, the distribution of the gas to be supplied is made uniform to prevent an abnormal discharge so that uniform etching having no variation can be carried out.Type: ApplicationFiled: June 21, 2002Publication date: December 26, 2002Applicant: Matsushita Electric Industrial Co., LTDInventors: Kiyoshi Arita, Tetsuhiro Iwai, Hiroshi Haji, Shoji Sakemi, Taiji Matano, Nobuhiro Satou -
Publication number: 20020197877Abstract: In a plasma treating apparatus, a ceramic porous substance having a three-dimensional network structure in which a frame portion 18a formed of ceramic containing alumina is provided continuously like a three-dimensional network is used for the material of an electrode member 17 for the plasma treating apparatus to be attached to the front surface of a gas supplying port of an electrode for plasma generation, and a gas for plasma generation is caused to pass through a hole portion 18b formed irregularly in the three-dimensional network structure. Consequently, the distribution of the gas to be supplied is made uniform to prevent an abnormal discharge so that uniform etching having no variation can be carried out.Type: ApplicationFiled: June 21, 2002Publication date: December 26, 2002Applicant: Matsushita Electric Industrial Co. Ltd.Inventors: Kiyoshi Arita, Tetsuhiro Iwai, Hiroshi Haji, Shoji Sakemi
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Publication number: 20020173161Abstract: A method of plasma-processing a silicon-based substrate provides a mirror-like etched surface of the substrate. A silicon wafer having a protective tape affixed to a circuit-formed side of the wafer is mounted on a mounting unit disposed within a process chamber of a plasma processing apparatus while the protective tape contacts on the mounting unit. The surface of the silicon wafer is kept at a temperature of 40° C. or above when the surface of the substrate is etched by plasma generated by plasma discharge in plasma-generating gas including fluorine-containing gas fed into the process chamber. This suppressing adhesion and accumulation of a reaction product of the fluorine-containing gas with respect to the surface to be etched, and consequently, provides the surface with uniform etching.Type: ApplicationFiled: March 1, 2002Publication date: November 21, 2002Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Kiyoshi Arita, Tetsuhiro Iwai
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Patent number: 6468351Abstract: A vacuum processing apparatus for performing plasma etching in a processing chamber on a base. An actuator, when lowered, forms a closed processing chamber by pressing a lid member onto a work platform, and, when raised, opens the processing chamber by setting the lid member apart from the work platform. The actuator is disposed above the lid member, and frame posts and conveying means, of the work are disposed so as not to block the front side of the lid member, and therefore a free working space for serviceman is kept at the front side of the lid member. Therefore, the serviceman can easily do maintenance work of the lid member or preparation of the processing chamber.Type: GrantFiled: June 7, 2000Date of Patent: October 22, 2002Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Kazuhiro Noda, Hiroshi Haji, Tetsuhiro Iwai
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Publication number: 20020148810Abstract: A surface treatment method for thinning a silicon based substrate obtains a milky-dull color on an overall surface uniformly of the silicon based substrate. To be more specific, a surface opposite to a circuit-formed surface is mechanically polished, then the surface is etched using inert gas such as argon gas for producing plasma. This etching forms micro dimples uniformly on the surface. Next, the surface is further etched using fluorine based gas for producing plasma. This etching obtains a milky-dull color uniformly on the surface. As a result, printed marks on the surface can be read with ease, and pick-up errors in die-bonding can be reduced.Type: ApplicationFiled: April 3, 2002Publication date: October 17, 2002Inventors: Kiyoshi Arita, Tetsuhiro Iwai, Hiroshi Haji, Shoji Sakemi
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Publication number: 20020090826Abstract: A method of plasma processing a silicon-containing object to be processed at a high etching rate without causing a surface of the object to have a hazy appearance, so that this surface can have an excellent visual quality. In the plasma processing method of etching the surface of the semiconductor wafer, gas containing sulfur hexafluoride and helium is used as a plasma-generating gas. A fluorine radical as an active substance which reacts with silicon of the surface of the semiconductor wafer, gaseous silicon tetrafluoride yielded by the reaction and a compound (SFn) of fluorine and sulfur that is generated as a reaction product are removed by the helium gas functioning as carrier gas. The helium gas prevents the reaction product from adhering to the surface of the wafer again.Type: ApplicationFiled: January 7, 2002Publication date: July 11, 2002Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Kiyoshi Arita, Tetsuhiro Iwai, Shoji Sakemi
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Patent number: 6340639Abstract: A plasma process apparatus performing an even plasma processing over the entire surface of a substrate, without accompanying thermal damage, and method of the plasma processing. In a process room 2, where a semiconductor wafer 4 is placed on a lower electrode 3 for processing with plasma, the semiconductor wafer 4 which has been fixed on a resin sheet 4a whose thermal expansion coefficient is greater than that of the semiconductor wafer 4 is pressed at the circumference edge by a substrate holding device 5 onto the surface of lower electrode 3. In such a setup, central portion of the semiconductor wafer can also be pressed onto the lower electrode 3 via the resin sheet 4a. Thus, there will be no gap between the surface of lower electrode 3 and the substrate, which contributes to eliminate thermal damages due to abnormally high temperature and to avoid a local discharge.Type: GrantFiled: October 24, 2000Date of Patent: January 22, 2002Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Kiyoshi Arita, Tetsuhiro Iwai, Hiroshi Haji
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Publication number: 20010021571Abstract: A semiconductor wafer processing apparatus grinds a surface of a semiconductor wafer by mechanical grinding, and then removes a damaged layer in the ground surface. In the processing apparatus, a grinding portion, a precenter portion, a wafer cleaning portion, plasma treatment portions, and magazines are arranged radially about an origin of a polar coordinate system of a third wafer transport portion having a robot mechanism, and their positions of arrangement are set such that the origin is located on lines of extension of wafer carry-in and carry-out center lines of the plasma treatment portions. Thus, the number of changed grippings of the semiconductor wafer can be minimized to prevent breakage of the semiconductor wafer. Moreover, transfer of the semiconductor wafer between the respective portions can be covered by the single robot mechanism, and the equipment can be made compact.Type: ApplicationFiled: February 26, 2001Publication date: September 13, 2001Inventors: Yutaka Koma, Kiyoshi Arita, Hiroshi Haji, Tetsuhiro Iwai