Abstract: A reconfigurable address generation circuit for image processing is configured to an arbitrary state based on configuration data generates a read address for reading out image data of pixel units having a plurality of rows and columns from a memory which stores image data. As the configuration data, there are set a X, Y count end value of the read out pixel unit, a width value of the image in the memory, and edge information for clip processing. The address generation circuit has X counter; Y counter; an X, Y clip processing circuits which convert the count value of the X, Y counter according to the left, right top and bottom edge information; and an address calcuration circuit which generates the reading out address, based on the count values from the X and Y clip processing circuits and the width value.

Abstract: The object of the present invention is to provide a method for producing carbonates capable of effectively and easily forming carbonates shaped to have an orientational birefringence and an aspect ratio greater than 1 as well as capable of controlling the particle size. For this end, it is a method of which a metallic ion source containing at least one selected from Sr2+ ions, Ca2+ ions, Ba2+ ions, Zn2+ ions, and Pb2+ with a carbonate source in a solution to thereby produce carbonates shaped to have an aspect ratio greater than 1, and the method include increasing the number of carbonate particles and increasing the volume of carbonate particles.

Abstract: To provide a process for producing carbonate particles, capable of efficient, easy formation of carbonate particles which have high crystallinity, less prone to agglomeration and offer orientation birefringence, particularly carbonate particles that are needle- or rod-shaped, and of controlling the particle size. In the process a metal ion source and a carbonate ion source are heated together in a liquid of 55° C. or higher for reaction to produce carbonate particles with an aspect ratio of greater than 1, wherein the metal ion source contains at least one metal ion selected from the group consisting of Sr2+, Ca2+, Ba2+, Zn2+ and Pb2+. The carbonate particles are preferably needle- or rod-shaped, pH of the liquid after heating reaction is preferably 8.20 or more, and in its X-ray diffraction spectrum the full-width at half maximum of the diffraction peak corresponding to (111) plane is preferably less than 0.8°.

Abstract: To provide a method for producing a carbonate, including: growing seed crystals, wherein the seed crystals are grown in a reaction solution containing at least urea. An aspect in which the seed crystals are strontium carbonate particles, an aspect in which the reaction solution contains a metal ion source and the metal ion source is a hydroxide of strontium, and the like are favorable.

Abstract: The present invention provides a method for producing carbonates, which includes at least adding an aqueous solution containing a carbonate source into an alcoholic solution containing a metal ion source, wherein an alkaline chemical is added when the carbonate source is reacted with the metal ion source.

Abstract: A distributed multimedia server system includes a buffer server module, a storage server module, and an intercluster connection network. Based on memory information on a buffer memory of the storage server module that stores divided multimedia information, the buffer server module obtains the divided multimedia information from the buffer memory using remote direct memory access. The storage server module reads the divided multimedia information requested from the buffer server module from a storage device, and stores the divided multimedia information in the buffer memory.

Abstract: An integrated circuit according to the invention includes a reconfigurable circuit including a plurality of computing units interconnected in a reconfigurable manner, and an input data controlling section. The input data controlling section controls input data such that the data is inputted to the reconfigurable circuit in response to a configuration of the reconfigurable circuit.

Abstract: Provided are target detection substrate for target detecting apparatuses capable of detecting various targets such as pathogens, biological substances and toxic substances without using a costly measuring apparatus; which can detect these targets with a low measurement error, high efficiency, simplicity, speed and sensitivity; and which can make a quantitative detection thereof. The target detection substrate includes at least a target interaction part which can interact with a target on an optical interference substrate, which optical interference substrate includes a substrate and a different refractive index film having a different refractive index from that of the substrate disposed on the substrate, and interferes irradiated light to radiate it as interference light where the total number of peak tops and peak bottoms in a graph of transmittance against wavelength of the interference light is from 1 to 20 in an arbitrary wavelength range of 100 nm.

Abstract: A reconfigurable circuit includes a network circuit for controlling connections between the output terminal and the input terminal of an arithmetic unit group, and a first selector connected between the arithmetic unit group and the network circuit. When a first control signal is in a first state, the first selector connects a first terminal of the arithmetic unit group to a first terminal of the network circuit, and also connects a second terminal of the arithmetic unit group to a second terminal of the network circuit. Meanwhile, when the first control signal is in a second state, the first selector connects the first terminal of the arithmetic unit group to the second terminal of the network circuit, and also connects the second terminal of the arithmetic unit group to the first terminal of the network circuit.

Abstract: A reconfigurable processor calculates execution times of configuration for executing pipeline processing from hardware configuration information, and fixes a clock cycle until processing ends. A counter compares the fixed clock cycle with the actual number of elapsed clocks, and, when the number of elapsed clocks equals the clock cycle, it is determined that pipeline processing has ended, and a configuration controller is notified of this.

Abstract: OCV coefficients in a path being an analysis target according to the number of gate stages are calculated in a coefficient arithmetically operating unit by canceling off a variation in delay in each gate in accordance with the number of gate stages in the target path, and timing analysis of the target path is performed in a timing analysis unit by using the OCV coefficient with the number of gate stages being considered, whereby a variation degree in the entire path is reduced in accordance with the number of gate stages in the target path, thus making it possible to carry out accurate timing analysis in consideration of the variation in a chip of a semiconductor integrated circuit.

Abstract: A reconfigurable address generation circuit for image processing is configured to an arbitrary state based on configuration data generates a read address for reading out image data of pixel units having a plurality of rows and columns from a memory which stores image data. As the configuration data, there are set a X, Y count end value of the read out pixel unit, a width value of the image in the memory, and edge information for clip processing. The address generation circuit has X counter; Y counter; an X, Y clip processing circuits which convert the count value of the X, Y counter according to the left, right top and bottom edge information; and an address calcuration circuit which generates the reading out address, based on the count values from the X and Y clip processing circuits and the width value.

Abstract: A reconfigurable processor calculates execution times of configuration for executing pipeline processing from hardware configuration information, and fixes a clock cycle until processing ends. A counter compares the fixed clock cycle with the actual number of elapsed clocks, and, when the number of elapsed clocks equals the clock cycle, it is determined that pipeline processing has ended, and a configuration controller is notified of this.

Abstract: A method for designing semiconductor integrated circuits that efficiently optimizes clock skews in a plurality of clock modes in the case of designing semiconductor integrated circuits having a plurality of clock modes. A plurality of clock paths in each of a plurality of clock modes are detected from layout data for a semiconductor integrated circuit. Delay time in all elements on each of the plurality of clock paths detected is collected. A delay adjustment position is set on each of the plurality of clock paths detected. An optimum delay value at the delay adjustment position on each of the plurality of clock paths is calculated by considering delay time at the set delay adjustment position as a nonnegative variable, by formulating a linear expression for each of the plurality of clock paths by use of this variable and the collected delay time in all of the elements, and by working out the linear expression.

Abstract: A reconfigurable operation apparatus consists of a plurality of operation units capable of reconfiguring themselves by using a piece of given first configuration data and of operating simultaneously with one another; RAMs; diverse processor elements required for constituting an operation apparatus; an inter-resource network interconnecting the operation units, the RAMs and the diverse processor elements, performing data transfers between resources connected thereto in a uniform transfer time independent of positions and kinds of the resources, and being reconfigurable by using a given second configuration data; and a configuration memory storing the first and the second configuration data. Configuration data is loaded from an external storage apparatus onto the configuration memory, and the first and the second configuration data are supplied to the reconfigurable processor resources in appropriate sequence and timing based on data available from a plurality of operation units.

Abstract: A semiconductor device includes a plurality of memories, a sequencer which outputs configuration information, and a memory reconfiguring circuit which reconfigures the memory area in accordance with the configuration information supplied from the sequencer. Since the memory reconfiguring circuit dynamically changes the allocation of the memories, it is possible to reconfigure the memory configuration and freely change the memory size in accordance with the purpose of use.

Abstract: A reconfigurable processor calculates execution times of configuration for executing pipeline processing from hardware configuration information, and fixes a clock cycle until processing ends. A counter compares the fixed clock cycle with the actual number of elapsed clocks, and, when the number of elapsed clocks equals the clock cycle, it is determined that pipeline processing has ended, and a configuration controller is notified of this.

Abstract: An operation apparatus includes a sequencer controlling states of a plurality of operation devices and a configuration memory storing therein configuration information as setting information for each state in the operation device. In the operation apparatus, a path which requires a data buffer and another path which requires no such a data buffer are provided for inputting data to the operation device, a data buffer control part is provided for controlling selection from these two paths and operation of the data buffer, and contents of path selection and operation control of the data buffer carried out by the data buffer control part are set according to the configuration information.

Abstract: A semiconductor device includes a configuration memory for storing configuration data, an arithmetic unit whose circuit configuration can be reconfigured in accordance with the configuration data, and a fixed value memory for storing fixed value data to be supplied to the arithmetic unit. Since the configuration data and fixed value data to be supplied to the arithmetic unit are stored in the different memories, no data area for storing the fixed value data need be set in the configuration memory. This makes it possible to supply a predetermined fixed value to the arithmetic unit by storing only information for reading out fixed value data from the fixed value memory.

Abstract: A reconfigurable processor in which an application can be switched more freely. A switching condition associating section associates output from a plurality of arithmetic and logic unit modules used as switching conditions for switching the operation of an arithmetic and logic unit group with a plurality of states indicative of switching condition codes. When a switching condition code output section decides that a switching condition comes into existence on the basis of the output from the plurality of arithmetic and logic unit modules set as the switching conditions, the switching condition code output section outputs a switching condition code corresponding to the switching condition which comes into existence. When a sequencer accepts the switching condition code, the sequencer switches the arithmetic and logic unit group to a state corresponding to the switching condition code.