Abstract: A data transfer control apparatus includes a memory, a write control part controlling data writing to the memory, a read control part controlling data reading from the memory, a read-start calculation part calculating an output timing of a notification which indicates a read-start operation to the read control part based on each transfer condition of the data writing to the memory and the data reading from the memory, and an asynchronous transfer part asynchronously transferring a clock of the notification, and notifying the read control part of the notification.

Abstract: Provided is a memory device in which the decrease of the effective bandwidth caused by the refresh operation of the memory device has been solved, a memory controller of the memory device, and a memory system thereof.

Abstract: An image memory, image memory system, and memory controller that are capable of efficiently accessing a rectangular area of two-dimensionally arrayed data are provided. The memory device has: a memory cell array that has a plurality of memory unit areas, each of which is selected by addresses; a plurality of input/output terminals; and an input/output unit provided between the memory cell array and the plurality of input/output terminals.

Abstract: Provided is a memory device in which the decrease of the effective bandwidth caused by the refresh operation of the memory device has been solved, a memory controller of the memory device, and a memory system thereof.

Abstract: The microreactor for mixing and discharging multiple raw material liquids is obtained by laminating: a base plate in which a raw material introducing fluid channel is formed; a raw material introducing plate; and a mixing fluid channel plate which is arranged between the base plate and the raw material introducing plate, and in which a mixing fluid channel is formed. The microreactor includes: a mixing fluid channel in the mixing fluid channel plate which is formed in the mixing fluid channel plate, and in which a flow is contracted in its width direction; and a mixing fluid channel in the base plate which is formed in the base plate, and which has a fluid channel cross-section which becomes larger in its depth direction as it goes downstream. The mixing fluid channel in the base plate communicates with the mixing fluid channel in the mixing fluid channel plate, and is connected to an outlet orifice from which to discharge the mixed liquids.

Abstract: An image memory, image memory system, and memory controller that are capable of efficiently accessing a rectangular area of two-dimensionally arrayed data are provided. The memory device has: a memory cell array that has a plurality of memory unit areas, each of which is selected by addresses; a plurality of input/output terminals; and an input/output unit provided between the memory cell array and the plurality of input/output terminals.

Abstract: An image memory, image memory system, and memory controller that are capable of efficiently accessing a rectangular area of two-dimensionally arrayed data are provided. The memory device has: a memory cell array that has a plurality of memory unit areas, each of which is selected by addresses; a plurality of input/output terminals; and an input/output unit provided between the memory cell array and the plurality of input/output terminals.

Abstract: Provided is a memory device in which the decrease of the effective bandwidth caused by the refresh operation of the memory device has been solved, a memory controller of the memory device, and a memory system thereof.

Abstract: Provided is a memory device in which the decrease of the effective bandwidth caused by the refresh operation of the memory device has been solved, a memory controller of the memory device, and a memory system thereof.

Abstract: The memory device has: a plurality of banks, each of which has a memory cell array having a plurality of page areas that are selected by row addresses respectively, and each of which is selected by a bank address; a row controller that controls activation of the page areas within each of the banks in response to a first operation code; and a group of data input/output terminals. A memory unit area within each of the activated page areas is accessed based on the column address. The row controller generates bank activation signals for the plurality of banks in response to multi-bank information data and a supplied bank address that are supplied along with the first command, and generates the row address of each of the plurality of banks in response to the supplied bank address and a supplied row address. The plurality of banks activate the page areas in response to the bank activation signals and the row addresses generated by the row address calculator.

Abstract: An NMR probe permits measurements to be made with its inner coil without replacing the probe. The NMR probe has three coils disposed to surround a sample tube. An inner coil can resonate with the HF and LF. An intermediate coil can resonate with the HF and LF, and produces an RF magnetic field perpendicular to the RF field produced by the inner coil. An outermost coil can resonate at least at a lock frequency. The outermost coil produces an RF magnetic field which is perpendicular to the RF field produced by the intermediate coil but which is coincident in direction with the RF field produced by the inner coil.

Abstract: The memory device has: a plurality of banks, each of which has a memory cell array having a plurality of page areas that are selected by row addresses respectively, and each of which is selected by a bank address; a row controller that controls activation of the page areas within each of the banks in response to a first operation code; and a group of data input/output terminals. A memory unit area within each of the activated page areas is accessed based on the column address. The row controller generates bank activation signals for the plurality of banks in response to multi-bank information data and a supplied bank address that are supplied along with the first command, and generates the row address of each of the plurality of banks in response to the supplied bank address and a supplied row address. The plurality of banks activate the page areas in response to the bank activation signals and the row addresses generated by the row address calculator.

Abstract: An arbiter circuit includes a priority coefficient calculating unit, a priority coefficient comparator an acceptance determining unit, and a priority determining unit. The priority coefficient calculating unit calculates for each request an arbitration priority coefficient based on a priority level set for each request by requesters. The priority coefficient comparator compares arbitration priority coefficients calculated for the requesters by the priority coefficient calculating unit. The acceptance determining unit determines whether to accept the requests based on the comparison result by the priority coefficient comparator. When the arbitration priority coefficient calculated by the priority coefficient calculating unit is equal between two or more requests, the priority determining unit determines a priority order for accepting the requests.

Abstract: An image memory, image memory system, and memory controller that are capable of efficiently accessing a rectangular area of two-dimensionally arrayed data are provided. The memory device has: a memory cell array that has a plurality of memory unit areas, each of which is selected by addresses; a plurality of input/output terminals; and an input/output unit provided between the memory cell array and the plurality of input/output terminals.

Abstract: An NMR probe permits measurements to be made with its inner coil without replacing the probe. The NMR probe has three coils disposed to surround a sample tube. An inner coil can resonate with the HF and LF. An intermediate coil can resonate with the HF and LF, and produces an RF magnetic field perpendicular to the RF field produced by the inner coil. An outermost coil can resonate at least at a lock frequency. The outermost coil produces an RF magnetic field which is perpendicular to the RF field produced by the intermediate coil but which is coincident in direction with the RF field produced by the inner coil.

Abstract: A data transfer control apparatus includes a memory, a write control part controlling data writing to the memory, a read control part controlling data reading from the memory, a read-start calculation part calculating an output timing of a notification which indicates a read-start operation to the read control part based on each transfer condition of the data writing to the memory and the data reading from the memory, and an asynchronous transfer part asynchronously transferring a clock of the notification, and notifying the read control part of the notification.

Abstract: The memory device has: a plurality of banks, each of which has a memory cell array having a plurality of page areas that are selected by row addresses respectively, and each of which is selected by a bank address; a row controller that controls activation of the page areas within each of the banks in response to a first operation code; and a group of data input/output terminals. A memory unit area within each of the activated page areas is accessed based on the column address. The row controller generates bank activation signals for the plurality of banks in response to multi-bank information data and a supplied bank address that are supplied along with the first command, and generates the row address of each of the plurality of banks in response to the supplied bank address and a supplied row address. The plurality of banks activate the page areas in response to the bank activation signals and the row addresses generated by the row address calculator.

Abstract: An image memory, image memory system, and memory controller that are capable of efficiently accessing a rectangular area of two-dimensionally arrayed data are provided. The memory device has: a memory cell array that has a plurality of memory unit areas, each of which is selected by addresses; a plurality of input/output terminals; and an input/output unit provided between the memory cell array and the plurality of input/output terminals.

Abstract: Provided is a memory device in which the decrease of the effective bandwidth caused by the refresh operation of the memory device has been solved, a memory controller of the memory device, and a memory system thereof.

Abstract: The memory device has: a plurality of banks, each of which has a memory cell array having a plurality of page areas that are selected by row addresses respectively, and each of which is selected by a bank address; a row controller that controls activation of the page areas within each of the banks in response to a first operation code; and a group of data input/output terminals. A memory unit area within each of the activated page areas is accessed based on the column address. The row controller generates bank activation signals for the plurality of banks in response to multi-bank information data and a supplied bank address that are supplied along with the first command, and generates the row address of each of the plurality of banks in response to the supplied bank address and a supplied row address. The plurality of banks activate the page areas in response to the bank activation signals and the row addresses generated by the row address calculator.