Patents by Inventor Tetsuo Suzuki

Tetsuo Suzuki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200110410
    Abstract: A device that processes map data used in self-position estimation of a mobile body including an external sensor, includes a processor and a memory that stores a computer program executable by the processor. The processor reads data from a storage device storing data of a two-dimensional map including a point cloud or occupied grids is stored according to a command of the computer program, extracts from the two-dimensional map one or more line segments defined by the point cloud or the occupied points on the two-dimensional map, selects at least one specific region from at least one region included in one or more line segments or at least one region defined by at least one pair of line segments, and associates additional data indicating a position of a specific region on the two-dimensional map with the data.
    Type: Application
    Filed: October 1, 2019
    Publication date: April 9, 2020
    Inventors: Takuya MURAI, Tetsuo SAEKI, Shinji SUZUKI
  • Publication number: 20200111433
    Abstract: According to an embodiment of the present invention, an active matrix substrate (100) includes a display region (DR) defined by a plurality of pixel regions (P) arranged in a matrix and a peripheral region (FR) located around the display region. The active matrix substrate includes a substrate (1), a first TFT (10), and a second TFT (20). The first TFT is supported by the substrate and disposed in the peripheral region. The second TFT is supported by the substrate and disposed in the display region. The first TFT includes a crystalline silicon semiconductor layer (11), which is an active layer. The second TFT includes an oxide semiconductor layer (21), which is an active layer. The first TFT and the second TFT each have a top-gate structure.
    Type: Application
    Filed: March 16, 2018
    Publication date: April 9, 2020
    Inventors: Tetsuo KIKUCHI, Hideki KITAGAWA, Hajime IMAI, Toshikatsu ITOH, Masahiko SUZUKI, Teruyuki UEDA, Kengo HARA, Setsuji NISHIMIYA, Tohru DAITOH
  • Patent number: 10593809
    Abstract: A semiconductor device includes a substrate and an oxide semiconductor TFT including an oxide semiconductor layer supported by the substrate and having a multilayer structure including a protective oxide semiconductor layer and a channel oxide semiconductor layer disposed closer to the substrate than the protective oxide semiconductor layer, an upper insulating layer on the oxide semiconductor layer, an upper gate electrode disposed on the upper insulating layer, an interlayer insulating layer covering the oxide semiconductor layer and the upper gate electrode, and first and second electrodes electrically connected to the oxide semiconductor layer, wherein a first opening extends through at least the interlayer insulating layer and the protective oxide semiconductor layer, and exposes a portion of the channel oxide semiconductor layer, and the first electrode is disposed on the interlayer insulating layer and within the first opening, and is in direct contact with, within the first opening, the portion.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: March 17, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Masahiko Suzuki, Tohru Daitoh, Hajime Imai, Tetsuo Kikuchi, Setsuji Nishimiya, Teruyuki Ueda, Kengo Hara
  • Publication number: 20200082884
    Abstract: A data write circuit of a resistive memory element is provided, the device being capable of writing with low writing energy using a simple circuit. The data write circuit of the resistive memory element, includes: a complementary resistive memory element; writing means for making the complementary resistive memory element cause a resistance change; detection means for detecting a writing state in the complementary resistive memory element; and control means for controlling writing by the writing means, based on a detected signal of the detection means.
    Type: Application
    Filed: October 31, 2017
    Publication date: March 12, 2020
    Inventors: TAKAHIRO HANYU, DAISUKE SUZUKI, HIDEO OHNO, TETSUO ENDOH
  • Publication number: 20200073189
    Abstract: [Object] To provide an active matrix substrate (1) that includes an organic insulating film (OIL) and first source layers (FSL2 to FSL4) and second source layers (SSL1 to SSL3), which constitute two-layer wiring lines, and that is produced with a high yield. [Solution] In an active matrix substrate (1), of the first source layers (FSL2 to FSL4) and the second source layers (SSL1 to SSL3), the second source layers (SSL1 to SSL3) arranged further from the substrate (2) are in contact with an organic insulating film (OIL) with a second inorganic insulating film (SINOIL) interposed therebetween.
    Type: Application
    Filed: August 23, 2019
    Publication date: March 5, 2020
    Inventors: Hitoshi TAKAHATA, Tohru DAITOH, Hajime IMAI, Tetsuo KIKUCHI, Kengo HARA, Masahiko SUZUKI, Setsuji NISHIMIYA, Teruyuki UEDA, Masamitsu YAMANAKA, Yoshihito HARA
  • Publication number: 20200058678
    Abstract: Provided is an active matrix substrate (100A) including: a gate metal layer (15) that has a two-layer structure composed of a Cu layer (15b) and a Ti layer (15a); a first insulating layer (16) on the gate metal layer (15); a source metal layer (18) that is formed on the first insulating layer (16) and has a two-layer structure composed of a Cu layer (18b) and a Ti layer (18a); a second insulating layer (19) on the source metal layer (18); a conductive layer (25) that is formed on the second insulating layer (19), and is in contact with the gate metal layer (15) within a first opening (16a1) formed in the first insulating layer (16) and is in contact with the source metal layer (18) within a second opening (19a2) formed in the second insulating layer (19); and a first transparent conductive layer (21) that is formed on the conductive layer (25) and includes any of a pixel electrode, a common electrode and an auxiliary capacitor electrode.
    Type: Application
    Filed: October 12, 2017
    Publication date: February 20, 2020
    Inventors: Teruyuki UEDA, Hideki KITAGAWA, Tohru DAITOH, Hajime IMAI, Masahiko SUZUKI, Setsuji NISHIMIYA, Tetsuo KIKUCHI, Toshikatsu ITOH, Kengo HARA
  • Publication number: 20200043955
    Abstract: A semiconductor device includes a first TFT, a first source-side connection section that is formed from a part of a second metal film and connected to a first source region, a first drain-side connection section that is formed from a part of the second metal film and connected to a first drain region, a second TFT that is driven by the first TFT, a second source-side connection section that is formed from a part of a first metal film and connected to a second source region, and a second drain-side connection section that is formed from a part of the first metal film or a second transparent electrode film and connected to a second drain region.
    Type: Application
    Filed: July 18, 2019
    Publication date: February 6, 2020
    Inventors: Masahiko SUZUKI, Tohru DAITOH, Hajime IMAI, Tetsuo KIKUCHI, Setsuji NISHIMIYA, Teruyuki UEDA, Masamitsu YAMANAKA, Kengo HARA
  • Publication number: 20200035717
    Abstract: A thin film transistor substrate includes a source line, a gate electrode, a channel region, a source region, a drain region, and a pixel electrode. The gate electrode is a portion of a first metal film disposed upper than a first insulating film that is disposed upper than a semiconductor film. The source line is a portion of a second metal film disposed upper than a second insulating film that is disposed upper than the first metal film. The channel region is a portion of a section of the semiconductor film and disposed to overlap the gate electrode. The source region is prepared by reducing a resistance of a section of the semiconductor film. The drain region is prepared by reducing a resistance of a section of the semiconductor film. The pixel electrode is prepared by reducing a resistance of a section of the semiconductor film.
    Type: Application
    Filed: July 11, 2019
    Publication date: January 30, 2020
    Inventors: Kengo HARA, Tohru DAITOH, Hajime IMAI, Tetsuo KIKUCHI, Masahiko SUZUKI, Setsuji NISHIMIYA, Teruyuki UEDA, Masamitsu YAMANAKA
  • Publication number: 20200027958
    Abstract: An active matrix substrate according to an embodiment of the present invention includes a plurality of thin film transistors supported on a substrate and an inorganic insulating layer covering the plurality of thin film transistors. Each thin film transistor includes a gate electrode, an oxide semiconductor layer, a gate insulating layer, a source electrode, and a drain electrode. At least one of the gate insulating layer and the inorganic insulating layer is an insulating layer stack having a multilayer structure including a silicon oxide layer and a silicon nitride layer. The insulating layer stack further includes an intermediate layer disposed between the silicon oxide layer and the silicon nitride layer, the intermediate layer having a refractive index nC higher than a refractive index nA of the silicon oxide layer and lower than a refractive index nB of the silicon nitride layer.
    Type: Application
    Filed: March 23, 2018
    Publication date: January 23, 2020
    Inventors: Masahiko SUZUKI, Hideki KITAGAWA, Tetsuo KIKUCHI, Toshikatsu ITOH, Setsuji NISHIMIYA, Teruyuki UEDA, Kengo HARA, Hajime IMAI, Tohru DAITOH
  • Publication number: 20200020756
    Abstract: An oxide semiconductor TFT (201) of an active matrix substrate includes an oxide semiconductor layer (107), an upper gate electrode (112) disposed on a part of the oxide semiconductor layer via a gate insulating layer, and a source electrode (113) and a drain electrode (114). As viewed from a normal direction of the substrate, the oxide semiconductor layer (107) includes a first portion (p1) that overlaps the upper gate electrode, and a second portion (p2) that is located between the first portion and the source contact region or drain contact region, such that the gate insulating layer does not cover the second portion. The upper gate electrode (112) has a multilayer structure including an alloy layer (112L) that is in contact with the gate insulating layer and a metal layer (112U) that is disposed on the alloy layer. The metal layer is made of a first metallic element M; the alloy layer is made of an alloy containing the first metallic element M; and the first metallic element M is Cu, Mo, or Cr.
    Type: Application
    Filed: March 19, 2018
    Publication date: January 16, 2020
    Inventors: Teruyuki UEDA, Hideki KITAGAWA, Tohru DAITOH, Hajime IMAI, Masahiko SUZUKI, Setsuji NISHIMIYA, Tetsuo KIKUCHI, Toshikatsu ITOH, Kengo HARA
  • Publication number: 20190371370
    Abstract: In reading of a memory unit, an read failure operation due to variation in characteristic of a transistor in a dynamic load is reduced. A read circuit that reads a voltage obtained by a voltage division of a dynamic load unit and the memory unit as an output of the memory unit includes the dynamic load unit having one end connected to a side of a power supply and the other end connected to a side of the memory unit, and a feedback unit that, by a feedback of the voltage obtained by the voltage division that is divided between the dynamic load unit and the memory unit, holds the voltage obtained by the voltage division. The dynamic load unit has an array structure in which a plurality of resistive memory elements are connected in series, in parallel, or in series-parallel. The dynamic load unit has the array structure of the resistive memory elements and this structure can suppress the read failure operation due to the variation in dynamic load.
    Type: Application
    Filed: December 18, 2017
    Publication date: December 5, 2019
    Inventors: Takahiro Hanyu, Daisuke Suzuki, Hideo Ohno, Tetsuo Endoh
  • Patent number: 10457143
    Abstract: In a fastening structure and an accelerator pedal device using the fastening structure, a screw is inserted into a screw insertion hole of a cover from a side of the cover facing away from a housing, and the screw is screwed into a screwing hole of a fastening portion of the housing. An annular space is provided between an edge of the screw insertion hole and the fastening portion.
    Type: Grant
    Filed: April 19, 2016
    Date of Patent: October 29, 2019
    Assignee: DENSO CORPORATION
    Inventors: Tetsuo Hariu, Haruhiko Suzuki, Takehiro Saito, Hiroshi Saji
  • Publication number: 20190326443
    Abstract: A semiconductor device includes a thin film transistor including a semiconductor layer, a gate electrode, a gate insulating layer, a source electrode, a drain electrode, the semiconductor layer includes a layered structure including a first oxide semiconductor layer including In and Zn, in which an atomic ratio of In with respect to all metallic elements included in the first oxide semiconductor layer is higher than an atomic ratio of Zn, a second oxide semiconductor layer including In and Zn, in which an atomic ratio of Zn with respect to all metallic elements included in the second oxide semiconductor layer is higher than an atomic ratio of In, and an intermediate oxide semiconductor layer arranged between the first oxide semiconductor layer and the second oxide semiconductor layer, and the first and second oxide semiconductor layers are crystalline oxide semiconductor layers, and the intermediate oxide semiconductor layer is an amorphous oxide semiconductor layer, and the first oxide semiconductor layer is
    Type: Application
    Filed: September 21, 2017
    Publication date: October 24, 2019
    Inventors: Masahiko SUZUKI, Hajime IMAI, Hideki KITAGAWA, Tetsuo KIKUCHI, Setsuji NISHIMIYA, Teruyuki UEDA, Kengo HARA, Tohru DAITOH, Toshikatsu ITOH
  • Patent number: 10450381
    Abstract: Various bispecific antibodies that specifically bind to both blood coagulation factor IX/activated blood coagulation factor IX and blood coagulation factor X and functionally substitute for the cofactor function of blood coagulation factor VIII, that is, the function to promote activation of blood coagulation factor X by activated blood coagulation factor IX, were produced. From these antibodies, multispecific antigen-binding molecules having a high activity of functionally substituting for blood coagulation factor VIII were successfully discovered.
    Type: Grant
    Filed: April 19, 2016
    Date of Patent: October 22, 2019
    Assignee: Chugai Seiyaku Kabushiki Kaisha
    Inventors: Tomoyuki Igawa, Zenjiro Sampei, Tetsuo Kojima, Tetsuhiro Soeda, Atsushi Muto, Takehisa Kitazawa, Yukiko Nishida, Chifumi Imai, Tsukasa Suzuki, Kazutaka Yoshihashi
  • Publication number: 20190315884
    Abstract: Various bispecific antibodies that specifically bind to both blood coagulation factor IX/activated blood coagulation factor IX and blood coagulation factor X and functionally substitute for the cofactor function of blood coagulation factor VIII, that is, the function to promote activation of blood coagulation factor X by activated blood coagulation factor IX, were produced. From these antibodies, multispecific antigen-binding molecules having a high activity of functionally substituting for blood coagulation factor VIII were successfully discovered.
    Type: Application
    Filed: July 2, 2019
    Publication date: October 17, 2019
    Applicant: Chugai Seiyaku Kabushiki Kaisha
    Inventors: Tomoyuki Igawa, Zenjiro Sampei, Tetsuo Kojima, Tetsuhiro Soeda, Atsushi Muto, Takehisa Kitazawa, Yukiko Nishida, Chifumi Imai, Tsukasa Suzuki, Kazutaka Yoshihashi
  • Publication number: 20190280126
    Abstract: A semiconductor device includes a thin film transistor, wherein: a semiconductor layer of the thin film transistor has a layered structure including a lower oxide semiconductor layer including In, Ga, Zn and Sn and an upper oxide semiconductor layer arranged on the lower oxide semiconductor layer and including In, Ga and Zn; a thickness of the lower oxide semiconductor layer is 20 nm or less; an atomic ratio of Sn with respect to all metal elements of the lower oxide semiconductor layer is 5% or more; the upper oxide semiconductor layer includes no Sn, or an atomic ratio of Sn with respect to all metal elements of the upper oxide semiconductor layer is smaller than an atomic ratio of Sn with respect to all metal elements of the lower oxide semiconductor layer; and a first angle ?1 between a side surface and a lower surface of the lower oxide semiconductor layer is smaller than a second angle ?2 between a side surface and a lower surface of the upper oxide semiconductor layer.
    Type: Application
    Filed: March 6, 2019
    Publication date: September 12, 2019
    Inventors: Tetsuo KIKUCHI, Masahiko SUZUKI, Setsuji NISHIMIYA, Teruyuki UEDA, Masamitsu YAMANAKA, Tohru DAITOH, Hajime IMAI, Kengo HARA
  • Patent number: 10381487
    Abstract: A thin film transistor includes a channel section formed from semiconductor material, a source electrode connected to one end of the channel section, a drain electrode connected to another end of the channel section, an upper gate electrode included in an upper layer than the channel section and overlapping the channel section, a lower gate electrode included in a lower layer than the channel section and overlapping the channel section, an upper gate insulation film disposed between the upper gate electrode and the channel section, and a lower gate insulation film disposed between the lower gate electrode and the channel section and having a film thickness relatively greater than that of the upper gate insulation film.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: August 13, 2019
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Kengo Hara, Tohru Daitoh, Hajime Imai, Tetsuo Kikuchi, Masahiko Suzuki, Setsuji Nishimiya, Teruyuki Ueda
  • Publication number: 20190236079
    Abstract: A search system includes a plurality of host side devices, a client side device, and an information provision device, the client side device includes a client side communication unit, a client side output section, and an acquisition unit, the host side device includes a host side communication unit, a host side output section, a proposal intention information generation unit generating proposal intention information, and a proposal information generation unit generating proposal information, and the information provision device includes a communication unit, a host summary DB storing host identification information and host summary information, a provision unit providing various information items, and a notification information generation unit generating notification information.
    Type: Application
    Filed: December 12, 2018
    Publication date: August 1, 2019
    Inventors: Tetsuo Shiwaku, Fumihiko MATSUMOTO, Kyoko KANEMATSU, Yutaka HASHIZUME, Masashi TSUNETOMI, Hirotaka SUZUKI
  • Patent number: 10355084
    Abstract: A semiconductor device includes a semiconductor chip, a cell surface electrode portion, and a peripheral edge surface structure portion. The semiconductor chip has a cell portion and a peripheral edge portion provided around the cell portion in plan view. The cell surface electrode portion is provided on the cell portion. The peripheral edge surface structure portion is provided on the peripheral edge portion. The peripheral edge portion is made thinner than the cell portion so that a back surface of the peripheral edge portion is more concave than a back surface of the cell portion. When the thickness of the cell portion is represented by tc and the size of the step between the cell portion and the peripheral edge portion on the back surface is represented by dtb, 0%<dtb/tc?1.5% is satisfied.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: July 16, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Koichi Nishi, Kenji Suzuki, Tetsuo Takahashi, Junichi Yamashita
  • Patent number: D867208
    Type: Grant
    Filed: October 9, 2017
    Date of Patent: November 19, 2019
    Assignees: Hitachi, Ltd., Central Japan Railway Company, A & F Corporation
    Inventors: Yukinobu Abe, Tohru Watanabe, Kiyoshi Morita, Takashi Furukawa, Yuuji Ueno, Yasuhide Ueda, Hajime Ito, Yuichi Ahiko, Hiroki Shimoyama, Tadashi Fujii, Hideto Sanui, Kyohei Suzuki, Tetsuo Fukuda, Ichiro Fukuda