Patents by Inventor Tetsuo Takahashi

Tetsuo Takahashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200303323
    Abstract: There is provided a semiconductor device having a structure that can suppress occurrence of chipping in a device region and that can reduce manufacturing cost of the semiconductor device. A semiconductor device includes a substrate and a first amorphous insulating film. The substrate has a main surface and an end surface. The main surface includes a peripheral region and a device region. The first amorphous insulating film is disposed on the peripheral region, and is separated from the device region. The first amorphous insulating film extends along the end surface in the form of a stripe. The first amorphous insulating film is flush with the end surface.
    Type: Application
    Filed: June 8, 2020
    Publication date: September 24, 2020
    Applicant: Mitsubishi Electric Corporation
    Inventors: Tetsuo TAKAHASHI, Masayoshi TARUTANI, Kazuhiko SAKUTANI, Kenji HARADA, Masao TAKATA, Kouichi IN
  • Publication number: 20200287030
    Abstract: A semiconductor device that includes transistor and diode regions in one semiconductor substrate achieves favorable tolerance during recovery behaviors of diodes. A semiconductor base includes an n?-type drift layer in the IGBT and diode regions. In the IGBT region, the semiconductor base includes a p-type base layer formed on the n?-type drift layer, a p+-type diffusion layer and an n+-type emitter layer formed selectively on the p-type base layer, the diffusion layer having a higher p-type impurity concentration than the p-type base layer, and gate electrodes facing the p-type base layer via a gate insulating film. In the diode region, the semiconductor base includes a p?-type anode layer formed on the n?-type drift layer. The p+-type diffusion layer has a higher p-type impurity concentration than the p?-type anode layer, and has a smaller depth and a lower p-type impurity concentration as approaching the diode region.
    Type: Application
    Filed: May 21, 2020
    Publication date: September 10, 2020
    Applicant: Mitsubishi Electric Corporation
    Inventors: Ryu KAMIBABA, Tetsuo TAKAHASHI, Akihiko FURUKAWA
  • Publication number: 20200287028
    Abstract: A semiconductor device includes a semiconductor substrate, and the semiconductor substrate is divided into an IGBT region, a diode region, and a MOSFET region. A drift layer of n?-type is provided in the semiconductor substrate. The drift layer is shared among the IGBT region, the diode region, and the MOSFET region. In the semiconductor substrate, the diode region is always disposed between the IGBT region and the MOSFET region to cause the IGBT region and the MOSFET region to be separated from each other without being adjacent to each other.
    Type: Application
    Filed: January 7, 2020
    Publication date: September 10, 2020
    Applicant: Mitsubishi Electric Corporation
    Inventors: Ryu KAMIBABA, Tetsuo TAKAHASHI, Shinya SONEDA
  • Publication number: 20200268712
    Abstract: An edaravone suspension for human oral administration includes edaravone particles, a dispersant, and water.
    Type: Application
    Filed: May 12, 2020
    Publication date: August 27, 2020
    Applicant: Mitsubishi Tanabe Pharma Corporation
    Inventors: Tetsuo Hayama, Tomohiro Takahashi, Tomoyuki Omura, Kouji Hayashi, Munetomo Matsuda, Tadashi Miyazawa
  • Patent number: 10756029
    Abstract: There is provided a semiconductor device having a structure that can suppress occurrence of chipping in a device region and that can reduce manufacturing cost of the semiconductor device. A semiconductor device includes a substrate and a first amorphous insulating film. The substrate has a main surface and an end surface. The main surface includes a peripheral region and a device region. The first amorphous insulating film is disposed on the peripheral region, and is separated from the device region. The first amorphous insulating film extends along the end surface in the form of a stripe. The first amorphous insulating film is flush with the end surface.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: August 25, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Tetsuo Takahashi, Masayoshi Tarutani, Kazuhiko Sakutani, Kenji Harada, Masao Takata, Kouichi In
  • Publication number: 20200264651
    Abstract: A signal processing device includes an oscillation circuit, a protection target circuit, a delay time detection circuit, and a clock control circuit. The oscillation circuit receives the frequency control signal and generates a clock signal having a frequency corresponding to the frequency control signal. According to the above-mentioned configuration, even when a delay failure due to aging occurs in the signal processing device, it is possible to prevent a malfunction.
    Type: Application
    Filed: February 6, 2020
    Publication date: August 20, 2020
    Inventors: Narihira TAKEMURA, Terunori KUBO, Tetsuo TAKAHASHI
  • Publication number: 20200259113
    Abstract: The present disclosure provides an electronic device including a plurality of first electrodes, a second electrode, a functional layer disposed between each first electrode and the second electrode, and an insulating layer having a slope portion on the first electrode, wherein the functional layer is continuously disposed so as to cover the first electrode, a neighboring first electrode, and the insulating layer covering the first electrode and the neighboring first electrode, the functional layer on the first electrode has a layer thickness smaller than a height from an upper surface of the first electrode to an upper surface of the insulating layer, and the functional layer on the slope portion of the insulating layer has a layer thickness of 20 nm or more in a direction perpendicular to a slope surface of the slope portion.
    Type: Application
    Filed: February 7, 2020
    Publication date: August 13, 2020
    Inventors: Tetsuo Takahashi, Norifumi Kajimoto, Koji Ishizuya, Hiroaki Sano, Hiroyuki Mochizuki
  • Patent number: 10734455
    Abstract: An organic device is provided. The device comprises a substrate and a plurality of light emitting elements formed on a first surface of the substrate. Each of the plurality of light emitting elements includes, from a side of the first surface, a first electrode, an organic layer formed on the first electrode and including a light emitting layer, and a second electrode formed on the organic layer. The organic device further comprises a third electrode formed between the first electrodes of adjacent light emitting elements of the plurality of light emitting elements, and an insulating layer covering a portion between the first electrode and the third electrode, an end portion of the first electrode, and an end portion of the third electrode. The insulating layer includes a recess between the first electrode and the third electrode.
    Type: Grant
    Filed: June 21, 2019
    Date of Patent: August 4, 2020
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Norifumi Kajimoto, Tetsuo Takahashi, Koji Ishizuya, Hiroaki Sano
  • Patent number: 10734506
    Abstract: A semiconductor device that includes transistor and diode regions in one semiconductor substrate achieves favorable tolerance during recovery behaviors of diodes. A semiconductor base includes an n?-type drift layer in the IGBT and diode regions. In the IGBT region, the semiconductor base includes a p-type base layer formed on the n?-type drift layer, a p+-type diffusion layer and an n+-type emitter layer formed selectively on the p-type base layer, the diffusion layer having a higher p-type impurity concentration than the p-type base layer, and gate electrodes facing the p-type base layer via a gate insulating film. In the diode region, the semiconductor base includes a p?-type anode layer formed on the n?-type drift layer. The p+-type diffusion layer has a higher p-type impurity concentration than the p?-type anode layer, and has a smaller depth and a lower p-type impurity concentration as approaching the diode region.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: August 4, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Ryu Kamibaba, Tetsuo Takahashi, Akihiko Furukawa
  • Patent number: 10720395
    Abstract: There is provided a semiconductor device having a structure that can suppress occurrence of chipping in a device region and that can reduce manufacturing cost of the semiconductor device. A semiconductor device includes a substrate and a first amorphous insulating film. The substrate has a main surface and an end surface. The main surface includes a peripheral region and a device region. The first amorphous insulating film is disposed on the peripheral region, and is separated from the device region. The first amorphous insulating film extends along the end surface in the form of a stripe. The first amorphous insulating film is flush with the end surface.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: July 21, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Tetsuo Takahashi, Masayoshi Tarutani, Kazuhiko Sakutani, Kenji Harada, Masao Takata, Kouichi In
  • Publication number: 20200168601
    Abstract: A semiconductor apparatus includes a semiconductor substrate and a second electrode. Semiconductor substrate includes a device region and a peripheral region. An n? drift region and second electrode extend from device region to peripheral region. An n buffer layer and a p collector layer are provided also in peripheral region. Peripheral region is provided with an n type region. N type region is in contact with second electrode and n buffer layer. The turn-off loss of the semiconductor apparatus is reduced.
    Type: Application
    Filed: October 1, 2019
    Publication date: May 28, 2020
    Applicant: Mitsubishi Electric Corporation
    Inventor: Tetsuo TAKAHASHI
  • Publication number: 20200161459
    Abstract: A switching element control device for controlling a switching element incorporating a reverse conducting diode is provided. The switching element control device includes: a voltage detection circuit detecting a voltage across first and second main electrodes of the switching element; a comparator circuit comparing the voltage detected by the voltage detection circuit with a threshold voltage; and a drive circuit controlling driving of the switching element. The comparator circuit controls the drive circuit so that an on signal is not provided to the switching element when the detected voltage exceeds the threshold voltage.
    Type: Application
    Filed: August 22, 2019
    Publication date: May 21, 2020
    Applicant: Mitsubishi Electric Corporation
    Inventors: Mitsuru KANEDA, Tetsuo TAKAHASHI, Shinya SONEDA, Ryu KAMIBABA
  • Publication number: 20200152911
    Abstract: There is provided a semiconductor device having a semiconductor element and a protective film that is disposed above the semiconductor element and contains silicon atoms and nitrogen atoms, wherein the protective film has an average number of nitrogen atoms bonded to one silicon atom of less than or equal to 1.35.
    Type: Application
    Filed: October 31, 2019
    Publication date: May 14, 2020
    Inventors: Tetsuo Takahashi, Koichi Ishige, Ryuji Ishii
  • Publication number: 20200150813
    Abstract: A system and method for input sensing comprises a display device having at least one piezoresistive sensing transistor. During a first period, a first resulting signal is received with a first data line by driving a first piezoresistive sensing transistor of a first subpixel of the display device with a first select signal. The first resulting signal corresponds to a change in resistance of the first piezoresistive sensing transistor. Further, at least one of force information and positional information associated with an input object may be determined at least partially based on the change in resistance.
    Type: Application
    Filed: November 13, 2018
    Publication date: May 14, 2020
    Inventors: Tetsuo TANEMURA, Seiki TAKAHASHI, Joseph Kurth REYNOLDS, Petr SHEPELEV
  • Publication number: 20200135717
    Abstract: A semiconductor device includes an IGBT as a switching element, and a diode. The IGBT includes: a p type channel doped layer formed in a surface layer part on a front side of a semiconductor substrate; a p+ type diffusion layer and an n+ type source layer individually selectively formed in a surface layer part of the p type channel doped layer; and an emitter electrode connected to the n+ type source layer and the p+ type diffusion layer. A part of the p type channel doped layer reaches a front-side surface of the semiconductor substrate and is connected to the emitter electrode. On the front-side surface of the semiconductor substrate, the p+ type diffusion layer is interposed between the p type channel doped layer and an n+ type source layer, and the p type channel doped layer and the n+ type source layer are not adjacent to each other.
    Type: Application
    Filed: September 13, 2019
    Publication date: April 30, 2020
    Applicant: Mitsubishi Electric Corporation
    Inventors: Tetsuo TAKAHASHI, Mitsuru KANEDA
  • Patent number: 10602080
    Abstract: A camera device generates a captured image, extracts flow line information relating to a staying position or a passing position of a moving object, and transmits the generated captured image and the extracted flow line information of the moving object to a server device for each predetermined transmission period. The server device generates a flow line analysis image in which the flow line information of the moving object is superimposed on the captured image and displays the generated flow line analysis image on a displayer. Furthermore, the server device switches a first flow line analysis image in a first predetermined period to a second flow line analysis image in a second predetermined period according to an operation of changing the period, and displays the resulting flow line analysis image.
    Type: Grant
    Filed: February 10, 2016
    Date of Patent: March 24, 2020
    Assignee: Panasonic I-PRO Sensing Solutions Co., Ltd.
    Inventors: Shinpei Hagisu, Tetsuo Tayama, Hidetoshi Kinoshita, Koji Yano, Manabu Nakamura, Takae Oguchi, Hideaki Takahashi
  • Patent number: 10567677
    Abstract: A camera device transmits a captured image and flow line information of moving objects to a server device for each predetermined transmission period. The server device generates a flow line analysis image in which the flow line information of the moving objects is superimposed on the captured image and displays the generated flow line analysis image on a display. The server device displays a first flow line analysis image generated based on a captured image and flow line information in a first period which is arbitrary designated, and receives an instruction by a user operation to shift the first period by an amount. The server device sets a second period by shifting the first period by the amount without changing a length in period, and displays a second flow line analysis image generated based on a captured image and flow line information in the second period.
    Type: Grant
    Filed: April 14, 2016
    Date of Patent: February 18, 2020
    Assignee: Panasonic i-PRO Sensing Solutions Co., Ltd.
    Inventors: Shinpei Hagisu, Tetsuo Tayama, Hidetoshi Kinoshita, Koji Yano, Manabu Nakamura, Takae Oguchi, Hideaki Takahashi
  • Publication number: 20200044065
    Abstract: A semiconductor device including a first conductivity type substrate, a first conductivity type carrier store layer formed on an upper surface side of the substrate, a second conductivity type channel dope layer formed on the carrier store layer, a first conductivity type emitter layer formed on the channel dope layer, a gate electrode in contact with the emitter layer, the channel dope layer and the carrier store layer via a gate insulating film, and a second conductivity type collector layer formed on a lower surface side of the substrate, wherein the gate insulating film has a first part in contact with the emitter layer and the channel dope layer, a second part in contact with the carrier store layer, and a third part in contact with the substrate, and at least a part of the second part is thicker than the first part and the third part.
    Type: Application
    Filed: October 9, 2019
    Publication date: February 6, 2020
    Applicant: Mitsubishi Electric Corporation
    Inventor: Tetsuo TAKAHASHI
  • Publication number: 20200034650
    Abstract: An apparatus includes a processor that matches of local-feature-amounts in a state where an image of a measurement target captured by an image-sensor and a projective-transformed image of three-dimensional design data of the measurement target substantially overlap each other on a display to search the captured image and a virtual image generated from the projective-transformed image for a plurality of feature-point pairs with similar local-feature-amounts of an image, estimates a temporary-external-parameter related to a position and orientation of the image-sensor, compares an initial-external-parameter and the temporary-external-parameter to diagnose reliability of the temporary-external-parameter, and selects, among the feature-point pairs, a specified number of feature-point pairs with a score value indicating similarity between two feature-points forming each feature-point pair equal to or higher than a threshold value, estimate a final-external-parameter using the selected feature-point pairs, and disp
    Type: Application
    Filed: July 8, 2019
    Publication date: January 30, 2020
    Applicant: FUJITSU LIMITED
    Inventors: Fumiyuki Takahashi, Tetsuo Koezuka
  • Patent number: 10541260
    Abstract: An organic photoelectric conversion element includes an anode, a cathode, and a photoelectric conversion portion between the anode and the cathode. The photoelectric conversion portion includes a first organic compound layer containing an organic compound. Also, a second organic compound layer is disposed between the cathode and the photoelectric conversion portion. The second organic compound layer contains an organic compound having an ionization potential of 5.1 eV or less and a band gap of 2.5 eV or more.
    Type: Grant
    Filed: May 24, 2016
    Date of Patent: January 21, 2020
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Jun Kamatani, Naoki Yamada, Masumi Itabashi, Yosuke Nishide, Hirokazu Miyashita, Tetsuya Kosuge, Satoru Shiobara, Tetsuo Takahashi, Akihiro Senoo, Kentaro Ito, Satoshi Ota