Patents by Inventor Tetsuo Takahashi
Tetsuo Takahashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7232260Abstract: A ferrule holder and a coil spring are provided in a main body formed in an approximately tube shape. A cable adaptor including a front opening part at a large diameter part is inserted from a back opening part into the main body having slits and. A first small diameter part of the main body fits with the large diameter part of the cable adaptor and prevents the cable adaptor from translating in the z-axis direction. And the second small diameter part of the main body controls transfer of the ferrule holder in the z-axis direction. At the forward part of the large diameter, a taper part which helps to insert the cable adaptor is formed around the circuit of the optical axis. Each slit formed at the back opening part also helps to insert the cable adaptor.Type: GrantFiled: April 14, 2005Date of Patent: June 19, 2007Assignee: Canare Electric Co., Ltd.Inventors: Tetsuo Takahashi, Manabu Komatsubara
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Publication number: 20070033680Abstract: An optical inspection system provided with a light source, object lens, illumination optical system emitting illumination light generated from the light source through an object lens to a sample, and imaging optical system forming an image of the sample projected by the object lens, the optical inspection system further provided with an imaging optical system magnification changer for changing the magnification of the imaging optical system and an illumination light cross-sectional dimension changer provided at the illumination optical system and changing the cross-sectional dimensions of the illumination light emitted to the sample in accordance with the magnification of the imaging optical system.Type: ApplicationFiled: July 13, 2006Publication date: February 8, 2007Inventor: Tetsuo Takahashi
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Patent number: 6998091Abstract: A large plastic blow-molded bottle of at least 64 oz., preferably 96 oz. or larger, is provided with an insert-type handle that preferably extends substantially within a maximum circumference of the bottle. The bottle has a height-to-width ratio of less than 2:1. Sufficient moldability is achieved by providing a vertical elongation magnification of approximately 2:1 and a horizontal elongation magnification of at least 3:1. The bottle can be round or rectangular in shape and may include a narrow side dimension (depth) of less than about 120 mm, allowing it to fit within the side pocket shelving of most refrigerators. The bottle may have a maximum total height of 265 mm or less so that it can fit on a standard sized shelf designed for a 64 oz. bottle.Type: GrantFiled: August 30, 2002Date of Patent: February 14, 2006Assignee: Yoshino Kogyosho Co., Ltd.Inventors: Takao Iizuka, Tetsuo Takahashi
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Publication number: 20050232549Abstract: A screwing part 1220 is inserted into a large through-hole 1110 from its front side and is screwed together with a male screw part of a jig. A convex part 1230 in an approximately ring shape is formed at a back end part of the screwing part 1220. The convex part 1230 is adjacent to a fitting part 1111 which is made of an approximately ring convex part projecting toward inside of the large through-hole 1110. The back of the fitting part 1111 is adjacent to a front end opening part 1310 of a back tubular part 1300. In short, the fitting part 1111 of the adaptor main body 1110 is sandwiched between the convex part 1230 and the front end opening part 1310. By inserting and pressing the back end opening part 1210 of the front tubular part 1200 into the front end opening part 1310 of the back tubular part 1300, the front tubular part 1200 and the back tubular part 1300 are connected and fixed with each other. Sign ? represents their pressing part.Type: ApplicationFiled: April 14, 2005Publication date: October 20, 2005Applicant: Canare Electric Co., Ltd.Inventors: Tetsuo Takahashi, Manabu Komatsubara
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Publication number: 20050232552Abstract: A ferrule holder 110 and a coil spring 120 are comprised in a main body 130 formed in an approximately tube shape. A cable adaptor 140 comprising a front opening part 142 at a large diameter part 141 is inserted from a back opening part 133 into the main body 130 having slits S2 and S3. A first small diameter part 131 of the main body 130 fits with the large diameter part 141 of the cable adaptor 140 and prevents the cable adaptor 140 from translating in the z-axis direction. And the second small diameter part 132 of the main body 130 controls transfer of the ferrule holder 110 in the z-axis direction. At the forward part of the large diameter 141, a taper part which helps to insert the cable adaptor 140 is formed around the circuit of the optical axis. Each slit formed at the back opening part 133 also helps to insert the cable adaptor 140.Type: ApplicationFiled: April 14, 2005Publication date: October 20, 2005Applicant: Canare Electric Co., Ltd.Inventors: Tetsuo Takahashi, Manabu Komatsubara
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Publication number: 20050167694Abstract: In a peripheral portion of an IGBT chip, an intermediate potential electrode (20) is provided between a field plate (14) and a field plate (15) on a field oxide film (13), to surround an IGBT cell. The intermediate potential electrode (20) is supplied with a prescribed intermediate potential between the potentials at an emitter electrode (10) and a channel stopper electrode (12) from intermediate potential applying means that is formed locally in a partial region on the chip peripheral portion.Type: ApplicationFiled: November 5, 2004Publication date: August 4, 2005Applicant: Mitsubishi Denki Kabushiki KaishaInventor: Tetsuo Takahashi
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Patent number: 6897493Abstract: A pin diode is formed by a p+ collector region, an n type buffer region, an n? region and an n+ cathode region. A trench is formed from the surface of n+ cathode region through n+ cathode region to reach n? region. An insulating film is formed along an inner wall surface of trench. A gate electrode layer is formed to oppose to the sidewall of n+ cathode region with insulating film interposed. A cathode electrode is formed to be electrically connected to n+ cathode region. An anode electrode is formed to be electrically connected to p+ collector region. The n+ cathode region is formed entirely over the surface between trenches extending parallel to each other. Thus, a power semiconductor device in which gate control circuit is simplified and which has good on property can be obtained.Type: GrantFiled: June 10, 2003Date of Patent: May 24, 2005Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Tetsuo Takahashi, Katsumi Nakamura, Tadaharu Minato, Masana Harada
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Patent number: 6888206Abstract: An n-type substrate surface and a p+ region are provided adjacent to each other, on upper surfaces of which an insulation film, a shield and a conductor are formed in this order. The shield is connected to the conductor. The shield and the conductor are insulated from the n-type substrate surface by the insulation film. Even when polarization occurs in a mold provided over a semiconductor device due to a potential distribution along the substrate surface of the semiconductor device, the conductive shield can prevent the substrate from being affected by the polarization in the mold, allowing avoidance of an adverse influence of deterioration in breakdown voltage and the like.Type: GrantFiled: November 21, 2002Date of Patent: May 3, 2005Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Tetsuo Takahashi, Hideki Takahashi
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Publication number: 20050062073Abstract: A pin diode is formed by a p+ collector region, an n type buffer region, an n? region and an n+ cathode region. A trench is formed from the surface of n+ cathode region through n+ cathode region to reach n? region. An insulating film is formed along an inner wall surface of trench. A gate electrode layer is formed to oppose to the sidewall of n+ cathode region with insulating film interposed. A cathode electrode is formed to be electrically connected to n+ cathode region. An anode electrode is formed to be electrically connected to p+ collector region. The n+ cathode region is formed entirely over the surface between trenches extending parallel to each other. Thus, a power semiconductor device in which gate control circuit is simplified and which has good on property can be obtained.Type: ApplicationFiled: November 2, 2004Publication date: March 24, 2005Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Tetsuo Takahashi, Katsumi Nakamura, Tadaharu Minato, Masana Harada
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Patent number: 6867437Abstract: A pin diode is formed by a p+ collector region, an n type buffer region, an n? region and an n+ cathode region. A trench is formed from the surface of n+ cathode region through n+ cathode region to reach n? region. An insulating film is formed along an inner wall surface of trench. A gate electrode layer is formed to oppose to the sidewall of n+ cathode region with insulating film interposed. A cathode electrode is formed to be electrically connected to n+ cathode region. An anode electrode is formed to be electrically connected to p+ collector region. The n+ cathode region is formed entirely over the surface between trenches extending parallel to each other. Thus, a power semiconductor device in which gate control circuit is simplified and which has good on property can be obtained.Type: GrantFiled: August 20, 2002Date of Patent: March 15, 2005Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Tetsuo Takahashi, Katsumi Nakamura, Tadaharu Minato, Masana Harada
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Patent number: 6757051Abstract: A projection optical system forms an image of an object in a first plane onto a second plane. The projection optical system has an optical element group including at least one refractive member and plural reflective members, and a plurality of lens-barrel units holding the optical element group divided into a plurality of respective groupings. The reflective members are all held by a single lens-barrel unit of the plurality of lens-barrels units.Type: GrantFiled: June 19, 2001Date of Patent: June 29, 2004Assignee: Nikon CorporationInventors: Tetsuo Takahashi, Jin Nishikawa, Yasuhiro Omura
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Patent number: 6693310Abstract: A pin diode is formed by a p+ collector region, an n type buffer region, an n− region and an n+ cathode region. A trench is formed from the surface of n+ cathode region through n+ cathode region to reach n− region. An insulating film is formed along an inner wall surface of trench. A gate electrode layer is formed to oppose to the sidewall of n+ cathode region with insulating film interposed. A cathode electrode is formed to be electrically connected to n+ cathode region. An anode electrode is formed to be electrically connected to p+ collector region. The n+ cathode region is formed entirely over the surface between trenches extending parallel to each other. Thus, a power semiconductor device in which gate control circuit is simplified and which has good on property can be obtained.Type: GrantFiled: May 23, 2001Date of Patent: February 17, 2004Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Tetsuo Takahashi, Katsumi Nakamura, Tadaharu Minato, Masana Harada
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Patent number: 6665049Abstract: The present invention is to provide a photomask which has a sufficient durability to short-wavelength exposure beams, too, and also can prevent any foreign matter from adhering to patterns for transfer. In a photomask on which a transfer pattern to be transferred to an exposure-target substrate 19 is formed and through which a stated exposure beam applied to a pattern surface 1P where the transfer pattern is formed is guided to a projection optical system PL for forming an image of the pattern, the photomask comprises a transmitting plate 3 disposed apart from the pattern surface by a stated interval d0 and having a stated thickness h and a transmission to the exposure beam, and the transmitting plate is substantially square and fulfills a stated condition.Type: GrantFiled: April 9, 2001Date of Patent: December 16, 2003Assignee: Nikon CorporationInventor: Tetsuo Takahashi
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Publication number: 20030218220Abstract: An n substrate surface (23o) and a p+ region (24) are provided adjacent to each other, on upper surfaces of which an insulation film (11), a shield (25) and a conductor (26) are formed in this order. The shield (25) is connected to the conductor (26). The shield and the conductor are insulated from the n- substrate surface (23o) by the insulation film (11). Even when polarization occurs in a mold provided over a semiconductor device due to a potential distribution along the substrate surface of the semiconductor device, the conductive shield (25) can prevent the substrate from being affected by the polarization in the mold, allowing avoidance of an adverse influence of deterioration in breakdown voltage and the like.Type: ApplicationFiled: November 21, 2002Publication date: November 27, 2003Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Tetsuo Takahashi, Hideki Takahashi
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Patent number: 6642994Abstract: Optical exposure apparatus and methods of using same, for patterning a workpiece and photo-cleaning the optical components in the apparatus, which can be contaminated by moisture and organic compounds in the atmosphere. The apparatus comprises an illumination optical system having a light source and one or more optical components, and a projection lens having an object plane and an image plane and one or more optical components. The optical exposure apparatus includes an exposure optical path or an exposure light beam through a predetermined space in the optical exposure system. An optical path deflection member for deflecting light is introduced into the exposure optical path so as to create a second optical path that differs from the exposure optical path. Also disclosed is a method of photo-cleaning the aforementioned optical components, including the steps of forming an exposure optical path and then changing this path to create a second optical path that differs from the exposure optical path.Type: GrantFiled: June 1, 2001Date of Patent: November 4, 2003Assignee: Nikon CorporationInventors: Takashi Mori, Tetsuo Takahashi, Hiroshi Nakamura, Yuji Kudo, Taro Ogata
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Publication number: 20030201455Abstract: A pin diode is formed by a p+ collector region, an n type buffer region, an n− region and an n+ cathode region. A trench is formed from the surface of n+ cathode region through n+ cathode region to reach n− region. An insulating film is formed along an inner wall surface of trench. A gate electrode layer is formed to oppose to the sidewall of n+ cathode region with insulating film interposed. A cathode electrode is formed to be electrically connected to n+ cathode region. An anode electrode is formed to be electrically connected to p+ collector region. The n+ cathode region is formed entirely over the surface between trenches extending parallel to each other. Thus, a power semiconductor device in which gate control circuit is simplified and which has good on property can be obtained.Type: ApplicationFiled: June 10, 2003Publication date: October 30, 2003Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Tetsuo Takahashi, Katsumi Nakamura, Tadaharu Minato, Masana Harada
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Patent number: 6639732Abstract: The present invention relates to a projection exposure apparatus (10) for and method of imaging a reticle (R) having patterned surface onto a substrate (W) in photolithographic processes for manufacturing a variety of devices. The invention further relates to an optical system (C) having a folding member (M1) suited to the projection exposure apparatus, and a method for manufacturing the optical system. The projection exposure apparatus comprises an illumination optical system (IS) and a reticle stage (RS) capable of holding the reticle so the normal line to its patterned surface is in the direction of gravity. The apparatus also includes a substrate stage (WS) capable of holding the substrate with its surface normal parallel to the direction of gravity. The optical system includes a first imaging optical system (A) comprising a concave reflecting mirror and a dioptric optical member arranged along a first optical axis. The first imaging optical system (A) forms an intermediate image of the patterned surface.Type: GrantFiled: December 6, 2002Date of Patent: October 28, 2003Assignee: Nikon CorporationInventors: Yasuhiro Omura, Tetsuo Takahashi, Masatoshi Ikeda, Shiwen Li
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Patent number: 6621557Abstract: Light from a pattern of a mask 3 travels through a first imaging optical system K1 to form a primary image I of the mask pattern. Light from the primary image I travels through a center aperture of a main mirror M1 and a lens component L2 to be reflected by a sub-mirror M2, and the light reflected by the sub-mirror M2 travels through the lens component L2 to be reflected by the main mirror M1. The light reflected by the main mirror M1 travels through the lens component L2 and a center aperture of the sub-mirror M2 to form a secondary image of the mask pattern at a reduction ratio on a surface of wafer 9.Type: GrantFiled: January 10, 2001Date of Patent: September 16, 2003Assignee: Nikon CorporationInventor: Tetsuo Takahashi
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Publication number: 20030160949Abstract: A method and illumination optical system forms a modified illumination configuration on an optical integrator so that a secondary light source having a desired modified illumination configuration is formed and light loss is minimized. A light beam shape changing element that diffuses illumination in a plurality of directions, and an angular light beam forming element that forms a plurality of light source images operate together to create a modified illumination configuration on the optical integrator. Since the secondary light source has a desired modified illumination configuration, an aperture stop used to restrict the size and/or shape of the secondary light source blocks only a small amount of illumination, or can be eliminated altogether.Type: ApplicationFiled: March 4, 2003Publication date: August 28, 2003Applicant: Nikon CorporationInventors: Hideki Komatsuda, Osamu Tanitsu, Akihiko Goto, Nobumichi Kanayamaya, Masato Shibuya, Tetsuo Takahashi
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Publication number: 20030137937Abstract: A capacity variable link apparatus including a main signal system and a control signal system is provided. The main signal system includes: an upper layer signal accommodation part; a lower layer path termination part; and a signal switching part for dividing the upper layer signal to lower layer signals in a lower layer path group having a capacity that is determined according to an amount of traffic of the upper layer signal. The control system includes: a traffic amount measuring part for measuring the amount of traffic of the upper layer and for determining whether the capacity of the lower layer path group is to be increased or decreased according to the amount; and a signal switching management part for controlling the signal switching part according to the result of the determination.Type: ApplicationFiled: January 21, 2003Publication date: July 24, 2003Applicant: NIPPON TELEGRAPH AND TELEPHONE CORP.Inventors: Yukio Tsukishima, Tetsuo Takahashi, Atsushi Watanabe, Yasutaka Okazaki