Patents by Inventor Tetsuo Takahashi
Tetsuo Takahashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20030137749Abstract: The present invention relates to a projection exposure apparatus (10) for and method of imaging a reticle (R) having patterned surface onto a substrate (W) in photolithographic processes for manufacturing a variety of devices. The invention further relates to an optical system (C) having a folding member (M1) suited to the projection exposure apparatus, and a method for manufacturing the optical system. The projection exposure apparatus comprises an illumination optical system (IS) and a reticle stage (RS) capable of holding the reticle so the normal line to its patterned surface is in the direction of gravity. The apparatus also includes a substrate stage (WS) capable of holding the substrate with its surface normal parallel to the direction of gravity. The optical system includes a first imaging optical system (A) comprising a concave reflecting mirror and a dioptric optical member arranged along a first optical axis. The first imaging optical system (A) forms an intermediate image of the patterned surface.Type: ApplicationFiled: December 6, 2002Publication date: July 24, 2003Applicant: Nikon CorporationInventors: Yasuhiro Omura, Tetsuo Takahashi, Masatoshi Ikeda, Shiwen Li
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Patent number: 6583856Abstract: Alignment is carried out between a mask and a wafer even during exposure as occasion demands, according to the movement of a pattern image caused by the positional fluctuation of a reflecting member. An exposure apparatus includes detection systems (13) and (14) for detecting the fluctuation amounts of reflecting members (M1) and (M2) from a reference position, and an arithmetic system (15) adapted to compute an amount of correction based on the detected fluctuation amounts, the amount of correction regarding at least one of the mask and the photosensitive substrate (4), and being necessary for substantial alignment between the pattern image formed in a moved state from a reference image-forming position and the photosensitive substrate (4). Based on the computed amount of correction, at least one of the mask and the photosensitive substrate is moved.Type: GrantFiled: September 6, 2000Date of Patent: June 24, 2003Assignee: Nikon CorporationInventor: Tetsuo Takahashi
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Patent number: 6563567Abstract: A method and illumination optical system forms a modified illumination configuration on an optical integrator so that a secondary light source having a desired modified illumination configuration is formed and light loss is minimized. A light beam shape changing element that diffuses illumination in a plurality of directions, and an angular light beam forming element that forms a plurality of light source images operate together to create a modified illumination configuration on the optical integrator. Since the secondary light source has a desired modified illumination configuration, an aperture stop used to restrict the size and/or shape of the secondary light source blocks only a small amount of illumination, or can be eliminated altogether.Type: GrantFiled: March 31, 2000Date of Patent: May 13, 2003Assignee: Nikon CorporationInventors: Hideki Komatsuda, Osamu Tanitsu, Akihiko Goto, Nobumichi Kanayamaya, Masato Shibuya, Tetsuo Takahashi
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Publication number: 20030006456Abstract: A pin diode is formed by a p+ collector region, an n type buffer region, an n− region and an n+ cathode region. A trench is formed from the surface of n+ cathode region through n+ cathode region to reach n− region. An insulating film is formed along an inner wall surface of trench. A gate electrode layer is formed to oppose to the sidewall of n+ cathode region with insulating film interposed. A cathode electrode is formed to be electrically connected to n+ cathode region. An anode electrode is formed to be electrically connected to p+ collector region. The n+ cathode region is formed entirely over the surface between trenches extending parallel to each other. Thus, a power semiconductor device in which gate control circuit is simplified and which has good on property can be obtained.Type: ApplicationFiled: August 20, 2002Publication date: January 9, 2003Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Tetsuo Takahashi, Katsumi Nakamura, Tadaharu Minato, Masana Harada
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Publication number: 20030006210Abstract: A large plastic blow-molded bottle of at least 64 oz., preferably 96 oz. or larger, is provided with an insert-type handle that preferably extends substantially within a maximum circumference of the bottle. The bottle has a height-to-width ratio of less than 2:1. Sufficient moldability is achieved by providing a vertical elongation magnification of approximately 2:1 and a horizontal elongation magnification of at least 3:1. The bottle can be round or rectangular in shape and may include a narrow side dimension (depth) of less than about 120 mm, allowing it to fit within the side pocket shelving of most refrigerators. The bottle may have a maximum total height of 265 mm or less so that it can fit on a standard sized shelf designed for a 64 oz. bottle.Type: ApplicationFiled: August 30, 2002Publication date: January 9, 2003Applicant: Yoshino Kogyosho Co., LtdInventors: Takao Iizuka, Tetsuo Takahashi
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Patent number: 6445012Abstract: A pin diode is formed by a p+ collector region, an n type buffer region, an n− region and an n+ cathode region. A trench is formed from the surface of n+ cathode region through n+ cathode region to reach n− region. An insulating film is formed along an inner wall surface of trench. A gate electrode layer is formed to oppose to the sidewall of n+ cathode region with insulating film interposed. A cathode electrode is formed to be electrically connected to n+ cathode region. An anode electrode is formed to be electrically connected to p+ collector region. The n+ cathode region is formed entirely over the surface between trenches extending parallel to each other. Thus, a power semiconductor device in which gate control circuit is simplified and which has good on property can be obtained.Type: GrantFiled: May 23, 2001Date of Patent: September 3, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Tetsuo Takahashi, Katsumi Nakamura, Tadaharu Minato, Masana Harada
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Patent number: 6397656Abstract: An operating frequency setting unit outputs an ultrasonic emitting command to a variable oscillator circuit in an operating frequency setting mode to cause a detector to emit an ultrasonic wave a plurality of times while varying the frequency thereof. At this time, emission or reflected waveform data are inputted via a band pass filter to detect a resonance frequency of a system including the piezoelectric element of the detector and an LPG tank on the basis of the difference between attenuation characteristics of waveforms. The detected resonance frequency is registered in a memory part as an operating frequency. Thus, it is possible to provide a general purpose ultrasonic sensor usable for any one of a plurality of vessels having any wall thickness and material when an object is detected while the detector is mounted on the outside face of a vessel.Type: GrantFiled: January 24, 2000Date of Patent: June 4, 2002Assignees: Yamatake Corporation, Kasuga Denki Kabushiki KaishaInventors: Hirotaro Yamaguchi, Osamu Suzuki, Yukio Katagishi, Huaigang Zang, Tetsuo Takahashi, Hidetaka Kizaki, Masao Iwamoto
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Publication number: 20020044260Abstract: A projection optical system forming an image of an object in a first plane onto a second plane, comprising, an optical element group including at least one refractive member and a plurality of reflective members, and a plurality of lens-barrel units holding the optical element group divided into a plurality of groupings, wherein the plurality of reflective members is all held by one lens-barrel unit of the plurality of lens-barrels units.Type: ApplicationFiled: June 19, 2001Publication date: April 18, 2002Applicant: NIKON CORPORATIONInventors: Tetsuo Takahashi, Jin Nishikawa, Yasuhiro Omura
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Patent number: 6362926Abstract: The present invention relates to a projection exposure apparatus (10) for and method of imaging a reticle (R) having patterned surface onto a substrate (W) in photolithographic processes for manufacturing a variety of devices. The invention further relates to an optical system (C) having a folding member(M1) suited to the projection exposure apparatus, and a method for manufacturing the optical system. The projection exposure apparatus comprises an illumination optical system (IS) and a reticle stage (RS) capable of holding the reticle so the normal line to its patterned surface is in the direction of gravity. The apparatus also includes a substrate stage (WS) capable of holding the substrate with its surface normal parallel to the direction of gravity. The optical system includes a first imaging optical system (A) comprising a concave reflecting mirror and a dioptric optical member arranged along a first optical axis. The first imaging optical system (A) forms an intermediate image of the patterned surface.Type: GrantFiled: November 27, 2000Date of Patent: March 26, 2002Assignee: Nikon CorporationInventors: Yasuhiro Omura, Yutaka Ichihara, Tetsuo Takahashi
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Publication number: 20010045566Abstract: A pin diode is formed by a p+ collector region, an n type buffer region, an n− region and an n+ cathode region. A trench is formed from the surface of n+ cathode region through n+ cathode region to reach n− region. An insulating film is formed along an inner wall surface of trench. A gate electrode layer is formed to oppose to the sidewall of n+ cathode region with insulating film interposed. A cathode electrode is formed to be electrically connected to n+ cathode region. An anode electrode is formed to be electrically connected to p+ collector region. The n+ cathode region is formed entirely over the surface between trenches extending parallel to each other. Thus, a power semiconductor device in which gate control circuit is simplified and which has good on property can be obtained.Type: ApplicationFiled: May 23, 2001Publication date: November 29, 2001Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Tetsuo Takahashi, Katsumi Nakamura, Tadaharu Minato, Masana Harada
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Publication number: 20010038446Abstract: Light from a pattern of a mask 3 travels through a first imaging optical system K1 to form a primary image I of the mask pattern. Light from the primary image I travels through a center aperture of a main mirror M1 and a lens component L2 to be reflected by a sub-mirror M2, and the light reflected by the sub-mirror M2 travels through the lens component L2 to be reflected by the main mirror M1. The light reflected by the main mirror M1 travels through the lens component L2 and a center aperture of the sub-mirror M2 to form a secondary image of the mask pattern at a reduction ratio on a surface of wafer 9.Type: ApplicationFiled: January 10, 2001Publication date: November 8, 2001Inventor: Tetsuo Takahashi
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Publication number: 20010030740Abstract: Optical exposure apparatus and methods of using same, for patterning a workpiece and photo-cleaning the optical components in the apparatus, which can be contaminated by moisture and organic compounds in the atmosphere. The apparatus comprises an illumination optical system having a light source and one or more optical components, and a projection lens having an object plane and an image plane and one or more optical components. The optical exposure apparatus includes an exposure optical path or an exposure light beam through a predetermined space in the optical exposure system. An optical path deflection member for deflecting light is introduced into the exposure optical path so as to create a second optical path that differs from the exposure optical path. Also disclosed is a method of photo-cleaning the aforementioned optical components, including the steps of forming an exposure optical path and then changing this path to create a second optical path that differs from the exposure optical path.Type: ApplicationFiled: June 1, 2001Publication date: October 18, 2001Applicant: NIKON CORPORATIONInventors: Takashi Mori, Tetsuo Takahashi, Hiroshi Nakamura, Yuji Kudo, Taro Ogata
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Patent number: 6268904Abstract: Optical exposure apparatus and methods of using same, for patterning a workpiece and photo-cleaning the optical components in the apparatus, which can be contaminated by moisture and organic compounds in the atmosphere. The apparatus comprises an illumination optical system having a light source and one or more optical components, and a projection lens having an object plane and an image plane and one or more optical components. The optical exposure apparatus includes an exposure optical path or an exposure light beam through a predetermined space in the optical exposure system. An optical path deflection member for deflecting light is introduced into the exposure optical path so as to create a second optical path that differs from the exposure optical path. Also disclosed is a method of photo-cleaning the aforementioned optical components, including the steps of forming an exposure optical path and then changing this path to create a second optical path that differs from the exposure optical path.Type: GrantFiled: November 19, 1998Date of Patent: July 31, 2001Assignee: Nikon CorporationInventors: Takashi Mori, Tetsuo Takahashi, Hiroshi Nakamura, Yuji Kudo, Taro Ogata
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Patent number: 6265735Abstract: A pin diode is formed by a p+ collector region, an n type buffer region, an n− region and an n+ cathode region. A trench is formed from the surface of n+ cathode region through n+ cathode region to reach n− region. An insulating film is formed along an inner wall surface of trench. A gate electrode layer is formed to oppose to the sidewall of n+ cathode region with insulating film interposed. A cathode electrode is formed to be electrically connected to n+ cathode region. An anode electrode is formed to be electrically connected to p+ collector region. The n+ cathode region is formed entirely over the surface between trenches extending parallel to each other. Thus, a power semiconductor device in which gate control circuit is simplified and which has good on property can be obtained.Type: GrantFiled: December 30, 1998Date of Patent: July 24, 2001Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Tetsuo Takahashi, Katsumi Nakamura, Tadaharu Minato, Masana Harada
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Patent number: 6195213Abstract: The present invention relates to a projection exposure apparatus (10) for and method of imaging a reticle (R) having patterned surface onto a substrate (W) in photolithographic processes for manufacturing a variety of devices. The invention further relates to an optical system (C) having a folding member (M1) suited to the projection exposure apparatus, and a method for manufacturing the optical system. The projection exposure apparatus comprises an illumination optical system (IS) and a reticle stage (RS) capable of holding the reticle so the normal line to its patterned surface is in the direction of gravity. The apparatus also includes a substrate stage (WS) capable of holding the substrate with its surface normal parallel to the direction of gravity. The optical system includes a first imaging optical system (A) comprising a concave reflecting mirror and a dioptric optical member arranged along a first optical axis. The first imaging optical system (A) forms an intermediate image of the patterned surface.Type: GrantFiled: June 8, 1999Date of Patent: February 27, 2001Assignee: Nikon CorporationInventors: Yasuhiro Omura, Tetsuo Takahashi, Masatoshi Ikeda, Shiwen Li, Yutaka Ichihara
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Patent number: 6188109Abstract: A buried sense electrode (8) having the same structure as that of a buried gate electrode (7) is provided in an n− layer (3) of an IGBT with a sense oxide film (10) interposed therebetween. The buried sense electrode (8) senses an electric potential of the n− layer (3). If an electric potential sensed by the buried sense electrode (8) is increased to exceed a gate threshold voltage of a MOSFET (21) having an n+ drain region (22), a p well region (23) and an n+ source region (24), the MOSFET (21) is turned ON. At this time, a gate voltage applied across a gate electrode (13) and an emitter electrode (11) of the IGBT is reduced to a value obtained by a sum of an ON-state voltage of the MOSFET (21), a breakdown voltage of a Zener diode (16) having an n+ cathode region (17) and a p+ anode region (18), and a forward voltage of a diode (19) having the p+ anode region (18) and an n+ cathode region (20).Type: GrantFiled: December 16, 1998Date of Patent: February 13, 2001Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Tetsuo Takahashi
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Patent number: 6152087Abstract: A boiler tube protector having a cylindrical or semi-cylindrical shape and adapted to be attached around an outer peripheral face of a boiler tube with mortar, which boiler tube protector includes a plurality of ceramic bodies closely arranged along their parting planes, wherein the parting planes includes a restraining portion for restraining slippage of each of the ceramic bodies.Type: GrantFiled: December 9, 1997Date of Patent: November 28, 2000Assignee: NGK Insulators, Ltd.Inventors: Toshio Shibata, Shigeo Ito, Kazuhiro Mizuno, Yasuhiro Terashima, Yuji Nakagawa, Keita Inoue, Norihiko Orita, Tetsuo Takahashi, Kazuo Yamamura
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Patent number: D438803Type: GrantFiled: October 8, 1998Date of Patent: March 13, 2001Assignees: Yoshino Kogyosho Co., Ltd., Ocean Spray Cranberries, Inc.Inventors: Tetsuo Takahashi, Hiroaki Sugiura, Fujio Shioiri, Shinji Shimada
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Patent number: D439521Type: GrantFiled: November 17, 1998Date of Patent: March 27, 2001Assignees: Yoshino Kogyosho Co., Ltd., Ocean Spray Cranberries, Inc.Inventors: Tetsuo Takahashi, Hiroaki Sugiura, Fujio Shioiri, Shinji Shimada
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Patent number: D439844Type: GrantFiled: November 17, 1998Date of Patent: April 3, 2001Assignees: Yoshino Kogyosho Co., Ltd., Ocean Spray Cranberries, Inc.Inventors: Tetsuo Takahashi, Hiroaki Sugiura, Fujio Shioiri, Shinji Shimada