Patents by Inventor Tetsuro Nakasugi

Tetsuro Nakasugi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110192300
    Abstract: According to one embodiment, an imprint method is disclosed. The method can include forming a liquid droplet of a transfer material with a volume greater than a predetermined reference volume by dropping the transfer material onto a major surface of a processing substrate. The method can include reducing the volume of the liquid droplet to be less than the reference volume by volatilizing the liquid droplet. In addition, the method can include filling the transfer material into a recess provided in a transfer surface of a template by bringing the liquid droplet having the volume reduced to be less than the reference volume into contact with the transfer surface of the template.
    Type: Application
    Filed: February 8, 2011
    Publication date: August 11, 2011
    Inventors: Masayuki Hatano, Ikuo Yoneda, Tetsuro Nakasugi, Kenji Ooki
  • Patent number: 7985958
    Abstract: According to an aspect of the invention, there is provided an electron beam drawing apparatus comprising at least one stage of a deflection amplifier and a deflection unit, a first storage section which stores shot information at a drawing time, a second storage section which stores a correction table indicating a relation between the shot information and an output voltage of the deflection amplifier, and an adjusting section which adjusts an output of the deflection amplifier based on the correction table stored in the second storage section and the shot information stored in the first storage section.
    Type: Grant
    Filed: November 8, 2005
    Date of Patent: July 26, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tetsuro Nakasugi, Kazuo Tawarayama, Hiroyuki Mizuno, Takumi Ota, Noriaki Sasaki, Tatsuhiko Higashiki, Takeshi Koshiba, Shunko Magoshi
  • Publication number: 20110097827
    Abstract: In one embodiment, a pattern formation method is disclosed. The method can place a liquid resin material on a workpiece substrate. The method can press a template against the resin material and measuring distance between a lower surface of a projection of the template and an upper surface of the workpiece substrate. The template includes a pattern formation region and a circumferential region around the pattern formation region. A pattern for circuit pattern formation is formed in the pattern formation region and the projection is formed in the circumferential region. The method can form a resin pattern by curing the resin material in a state of pressing the template. In addition, the method can separate the template from the resin pattern.
    Type: Application
    Filed: September 15, 2010
    Publication date: April 28, 2011
    Inventors: Masayuki HATANO, Suigen Kyoh, Tetsuro Nakasugi
  • Patent number: 7889910
    Abstract: A character pattern extracting method includes ranking character patterns whose number is larger than a maximum number of character patterns in an aperture, depending on the number of reference times in design data of a semiconductor device, extracting first extraction patterns whose number is smaller than the maximum number from the large number of read character patterns in a descending order of the reference time number, defining character patterns except the first extraction patterns out of the larger number of character patterns as candidate patterns, selecting from the candidate patterns a plurality of candidate patterns whose number corresponds to a difference between the number of extracted patterns from the maximum number, and creating combinations of the selected candidate patterns, and extracting second extraction patterns included in a combination among the combinations of candidate patterns, in which a manufacturing time of the semiconductor device is most shortened.
    Type: Grant
    Filed: May 4, 2007
    Date of Patent: February 15, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tetsuro Nakasugi, Takumi Ota, Takeshi Koshiba, Noriaki Sasaki
  • Publication number: 20100264113
    Abstract: There is provided a template in which a gap region of a substrate to be processed can be covered with an imprint resist, a method of manufacturing the same, and a method of forming a pattern. A template used in an optical imprint method includes a substrate, a pattern forming region that is provided on the substrate and includes an imprint pattern, a first step portion that is provided outside the pattern forming region and is disposed below the pattern forming region, a first side portion that connects the pattern forming region and the first step portion, a second step portion that is provided outside the first step portion and is disposed below the first step portion, and a second side portion that connects the first step portion and the second step portion and has a surface roughness more than that of the first side portion.
    Type: Application
    Filed: March 16, 2010
    Publication date: October 21, 2010
    Inventors: Ikuo YONEDA, Takuya Kono, Tetsuro Nakasugi, Ryoichi Inanami
  • Publication number: 20100237045
    Abstract: A pattern forming method includes determining an amount of curable resin to be formed on a substrate, the curable resin having volatility, the amount of the curable resin being determined by a calculation considering volatile loss of the curable resin, the calculation being performed for each of a plurality of regions of the substrate, forming the curable resin having the determined amount on the substrate, the forming the curable resin being performed for each of the plurality of regions of the substrate, contacting the curable resin formed on the substrate with a template, the template including a pattern to be filled with the curable resin by the contacting, and curing the curable resin under a condition where the curable resin is in contact with the template.
    Type: Application
    Filed: March 18, 2010
    Publication date: September 23, 2010
    Inventors: Takeshi KOSHIBA, Ikuo Yoneda, Tetsuro Nakasugi
  • Publication number: 20100078860
    Abstract: An imprint method includes applying a light curable resin on a substrate to be processed, the substrate including first and second regions on which the light curable resin is applied, contacting an imprint mold with the light curable resin, curing the light curable resin by irradiating the light curable resin with light passing through the imprint mold, generating gas by performing a predetermined process to the light curable resin applied on a region of the substrate, the region including at least the first region, wherein an amount of gas generated from the light curable resin applied on the first region is larger than an amount of gas generated from the light curable resin of the second region, and forming a pattern by separating the imprint mold from the light curable resin after the gas being generated.
    Type: Application
    Filed: September 21, 2009
    Publication date: April 1, 2010
    Inventors: Ikuo Yoneda, Kentaro Matsunaga, Yukiko Kikuchi, Yoshihisa Kawamura, Eishi Shiobara, Shinichi Ito, Tetsuro Nakasugi, Hirokazu Kato
  • Publication number: 20100075443
    Abstract: A template inspection method for performing defect inspection of a template, by bringing a pattern formation surface of a template used to form a pattern close to a first fluid coated on a flat substrate, filling the first fluid into a pattern of the template, and by performing optical observation of the template in a state that the first fluid is sandwiched between the template and the substrate, wherein a difference between an optical constant of the first fluid and an optical constant of the template is larger than a difference between an optical constant of air and the optical constant of the template.
    Type: Application
    Filed: September 3, 2009
    Publication date: March 25, 2010
    Inventors: Ikuo YONEDA, Tetsuro Nakasugi, Masamitsu Itoh, Ryoichi Inanami
  • Publication number: 20100023146
    Abstract: A control method for a semiconductor manufacturing apparatus, comprising: generating, as log data, a history of operation states of the semiconductor manufacturing apparatus when a wafer is processed by the semiconductor manufacturing apparatus; specifying, based on the log data, processing results in which operation states of the semiconductor manufacturing apparatus are abnormal states out of processing results after the processing of the wafer processed by the semiconductor manufacturing apparatus as abnormal processing results; creating control data for the semiconductor manufacturing apparatus based on the processing results and the abnormal processing results; and controlling the processing by the semiconductor manufacturing apparatus using the control data.
    Type: Application
    Filed: July 2, 2009
    Publication date: January 28, 2010
    Inventors: Masayuki HATANO, Tetsuro NAKASUGI
  • Patent number: 7648809
    Abstract: An EB exposure method includes dividing drawing layer pattern to be transferred onto drawing layer by EB exposure and underlying pattern to be transferred onto an underlying layer of the drawing layer by the EB exposure respectively into unit regions, setting representative figure in each of the unit regions of the drawing and underlying layers, the representative figure set in each of the unit regions of the drawing layer corresponding to the drawing layer pattern of each of the unit regions of the drawing layer, the representative figure set in each of the unit regions of the underlying layer corresponding to the underlying layer pattern of each of the unit regions of the underlying layer, and obtaining influence of proximity effect of an arbitrary region of the drawing layer pattern, based on the representative figure that corresponds to the drawing and underlying layer patterns.
    Type: Grant
    Filed: August 16, 2006
    Date of Patent: January 19, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tetsuro Nakasugi
  • Publication number: 20090315223
    Abstract: A template includes a substrate, an element pattern formed on a surface of the substrate, and a light absorbing portion formed on or inside the substrate.
    Type: Application
    Filed: June 12, 2009
    Publication date: December 24, 2009
    Inventors: Ikuo Yoneda, Shinji Mikami, Takumi Ota, Tetsuro Nakasugi
  • Publication number: 20090267267
    Abstract: An imprint method includes contacting a template on a substrate, the template including a pattern to be transferred on the substrate, separating the template from the substrate, and removing particle adhered on the template before contacting the template on the substrate, the removing the particle including pressing the template on an adhesive member and separating the pressed template from the adhesive member, wherein adhesiveness of the adhesive member to the template is higher than adhesiveness of the adhesive member to the substrate.
    Type: Application
    Filed: April 20, 2009
    Publication date: October 29, 2009
    Inventors: Ikuo Yoneda, Tetsuro Nakasugi, Shinji Mikami
  • Publication number: 20090246709
    Abstract: A manufacturing method of a semiconductor device includes preparing a first circuit pattern original plate including a first pattern part of a mark pattern, preparing a second circuit pattern original plate including a second pattern part of the mark pattern, transferring the first pattern part to a mask film on an underlying area to form a first transfer pattern part in the mask film, transferring the second pattern part to the mask film to form a second transfer pattern part in the mask film, and patterning the underlying area by using the mask film including a transfer mark pattern, which is obtained by combining the first transfer pattern part and the second transfer pattern part, as a mask to form an underlying mark pattern in the underlying area.
    Type: Application
    Filed: March 19, 2009
    Publication date: October 1, 2009
    Inventors: Tetsuro NAKASUGI, Takashi SATO, Kazutaka ISHIGO
  • Publication number: 20090206280
    Abstract: The first charged-beam optical system, which is one of the charged-beam optical systems, detects first marks provided on the chips formed in the wafer. The positions of the chips made in the wafer are calculated from position data about the first marks detected. The charged-beam optical systems detect the second mark provided on a stage. The position of the beam generated by each charged-beam optical system is adjusted in accordance with position data about the second mark detected. The charged-beam optical systems are used in accordance with the positions of the chips, to thereby draw a pattern.
    Type: Application
    Filed: January 30, 2009
    Publication date: August 20, 2009
    Inventors: Takeshi KOSHIBA, Tetsuro NAKASUGI, Ryoichi INANAMI, Takumi OTA, Hiroyuki MIZUNO
  • Publication number: 20090148782
    Abstract: An exposure method includes setting a photo mask into an exposure apparatus. The exposure apparatus includes an opening/closing unit configured to block a part of exposure light from a light source to the wafer. The photo mask having a product area in which a pattern to be used when a central part of a wafer is exposed is formed and peripheral exposure areas in each of which a pattern to be used when a peripheral area is exposed is formed. The peripheral exposure areas are formed to have a plurality of types of pattern densities. Then, a peripheral part of the wafer exposed. When exposing, the opening/closing unit is opened such that one or more of exposed photo mask areas selected from among the peripheral exposure areas has a pattern density corresponding to a shot position of the peripheral part.
    Type: Application
    Filed: December 9, 2008
    Publication date: June 11, 2009
    Inventors: Takuya Kono, Tetsuro Nakasugi, Masamitsu Ito, Tatsuhiko Higashiki
  • Publication number: 20090095711
    Abstract: A microfabrication apparatus for pressing an original plate including a pattern down on a substrate to transfer the pattern on the substrate includes a first measurement unit for measuring relative positional displacement between the substrate and the plate above the substrate, a position correction unit for correcting relative position between the substrate and the plate such that the pattern is to be transferred on a first predetermined position of the substrate based on the relative positional displacement measured by the first measurement unit, a pressing unit for pressing the plate above the substrate down on the substrate to transfer the pattern on the substrate in a state that the relative positional displacement between the substrate and the plate is corrected by the position correction unit, and a second measurement unit for measuring relative positional relationship between the pattern transferred on the substrate and a pattern previously formed on the substrate.
    Type: Application
    Filed: September 25, 2008
    Publication date: April 16, 2009
    Inventors: Takeshi Koshiba, Yumi Nakajima, Tetsuro Nakasugi, Kazuo Tawarayama, Ikuo Yoneda, Hiroyuki Mizuno
  • Patent number: 7482604
    Abstract: According to an aspect of the invention, there is provided an electron beam lithography apparatus including a first setting unit configured to set a drawing position on a semiconductor substrate based on layout information of the semiconductor substrate, a second setting unit configured to set a valid range on the semiconductor substrate based on shape information of the semiconductor substrate, a determination unit configured to determine whether or not the drawing position falls within the valid range, and an irradiation unit configured to irradiate the semiconductor substrate with an electron beam when the determination unit determines that the drawing position falls within the valid range.
    Type: Grant
    Filed: May 9, 2006
    Date of Patent: January 27, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tetsuro Nakasugi, Noriaki Sasaki, Takeshi Koshiba, Takumi Ota
  • Patent number: 7459705
    Abstract: A charged particle beam exposure method is disclosed, which includes preparing an aperture mask having character apertures, correcting dimensions of designed patterns in design data in consideration of at least one of factors such as a forward scattering distance of a charged particle, a rearward scattering distance of the charged particle, a blurring of a beam of the charged particle, a dimension conversion difference of the designed patterns due to a denseness/coarseness difference of the designed patterns caused when the underlayer is processed while using the resist as a mask, and the like, allocating at least a part of a specified character aperture of the plurality of character apertures of the aperture mask to the corrected designed patterns to produce writing data, and exposing the resist to the beams of the charged particle passed through the at least a part of the specified character aperture based on the writing data.
    Type: Grant
    Filed: October 19, 2006
    Date of Patent: December 2, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tetsuro Nakasugi, Ryoichi Inanami, Takumi Ota, Takeshi Koshiba
  • Patent number: 7435978
    Abstract: A system for correcting a charged particle beam lithography condition including: an error calculation unit configured to calculate an error in an illumination position of a charged particle beam, the charged particle beam is controlled by a lithography condition corrected by initial correction parameters; a temporary correction unit configured to calculate temporary correction parameters to decrease the error to a minimum; and a main correction unit configured to calculate main correction parameters correcting the lithography condition, by executing statistical processing using the temporary correction parameters and the initial correction parameters.
    Type: Grant
    Filed: September 30, 2005
    Date of Patent: October 14, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tetsuro Nakasugi, Takumi Ota
  • Patent number: 7368737
    Abstract: An electron beam writing method is disclosed, which includes preparing electron beam writing data structured from writing pattern data expressed by both data of VSB shots which are units of shaping beams at the time of carrying out writing a pattern and data of CP shots serving as bases of a repeating pattern, and CP aperture data into which identification numbers IDs and opening positions of respective openings of a CP aperture having openings for VSB shots and openings for CP shots are described, inputting the electron beam writing data to an electron beam writing apparatus, and expanding the electron beam writing data into data of the respective shots defined in the electron beam writing data, determining irradiation times of the respective expanded shots while correcting shot positions, and outputting control signals corresponding to shot data to repeat a shot of a desired pattern, by the electron beam writing apparatus.
    Type: Grant
    Filed: April 25, 2006
    Date of Patent: May 6, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ryoichi Inanami, Tetsuro Nakasugi