Patents by Inventor Tetsushi Koide

Tetsushi Koide has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230214970
    Abstract: Local image enhancement processing is executed on an image obtained by imaging a transcription material. The enhanced image is divided into a plurality of patch images and input to a machine learning identifier. The patch images after segmentation output from the machine learning identifier are combined to generate a likelihood map image of skin ridges from the whole image based on a result of the segmentation. Binarization processing is executed on the likelihood map image to generate a binary image. A skin ridge region is extracted based on the binary image to calculate the area of the skin ridge region.
    Type: Application
    Filed: March 11, 2023
    Publication date: July 6, 2023
    Inventors: Tetsushi KOIDE, Michihiro HIDE, Yumi AOYAMA
  • Publication number: 20220145233
    Abstract: Provided is a technique for preventing erroneous recognition of a fine particle region from a captured image of fine particles. A fine particle testing apparatus of the present disclosure includes: an imaging part capturing a first fine particle image of a well that holds a liquid containing fine particles; an image processor executing a process of generating a second fine particle image by extracting a contour of the first fine particle image, a process of performing a logical operation between the first fine particle image and the second fine particle image, a process of calculating a feature amount of the fine particles based on a result of the logical operation, and a process of determining growth of the fine particles in the well based on the calculated feature amount; and an output part outputting a result of the determination.
    Type: Application
    Filed: March 4, 2019
    Publication date: May 12, 2022
    Applicant: HITACHI HIGH-TECH CORPORATION
    Inventors: Kiyotaka SUGIYAMA, Tetsushi KOIDE, Chihiro UEMATSU, Hiroko FUJITA, Akira MASUYA
  • Publication number: 20210010054
    Abstract: Provided is a technique that enables accurate determination as to whether growth of bacteria has occurred or been inhibited. A bacteria test apparatus according to the present disclosure includes a microscope optical system which captures images of bacteria in each of a plurality of wells at a plurality of time points, the plurality of wells each holding a culture solution containing an antibacterial drug and the bacteria, an arithmetic unit which calculates a feature of luminance value for each of the images of the bacteria, a determination unit which determines whether growth of the bacteria has occurred in the wells based on a change in the feature of luminance value, and a display device which displays a determination result output from the determination unit. The arithmetic unit calculates, as the feature of luminance value, a feature including at least one of a mean, a median, or a mode (see FIG. 4).
    Type: Application
    Filed: January 24, 2019
    Publication date: January 14, 2021
    Inventors: Yuichi UCHIHO, Chihiro UEMATSU, Tetsushi KOIDE
  • Patent number: 10062161
    Abstract: An endoscopic image diagnosis support system (100) includes: a memory (10) that stores learning images pre-classified into pathological types; and a processor (20) that, given an endoscopic image, performs feature value matching between an image of an identification target region in the endoscopic image and the learning images, to identify the pathological types in the identification target region.
    Type: Grant
    Filed: February 2, 2015
    Date of Patent: August 28, 2018
    Assignee: HIROSHIMA UNIVERSITY
    Inventors: Tetsushi Koide, HoangAnh Tuan, Shigeto Yoshida, Tsubasa Mishima, Satoshi Shigemi, Toru Tamaki, Tsubasa Hirakawa, Rie Miyaki, Kouki Sugi
  • Patent number: 9959473
    Abstract: In a symbol recognition device, each histogram computation module receives an image of each partial region of a recognition target region in a binarized image and computes a frequency distribution of pixels of a given color in each line or column in the partial region; each run length determination module receives an image of each partial region of the recognition target region and determines whether or not a line or column of pixels of the given color having a certain length is present in the partial region; a control module feeds pixel information of the partial regions, read by scanning the binarized image stored in the image memory, into the histogram computation modules and the run length determination modules; a determination module determines a symbol included in the binarized image based on computation results of the histogram computation modules and determination results of the run length determination modules.
    Type: Grant
    Filed: March 29, 2016
    Date of Patent: May 1, 2018
    Assignee: HIROSHIMA UNIVERSITY
    Inventors: Tetsushi Koide, Hoang Anh Tuan, Masaharu Yamamoto, Tsubasa Mishima
  • Publication number: 20160350912
    Abstract: An endoscopic image diagnosis support system (100) includes: a memory (10) that stores learning images pre-classified into pathological types; and a processor (20) that, given an endoscopic image, performs feature value matching between an image of an identification target region in the endoscopic image and the learning images, to identify the pathological types in the identification target region.
    Type: Application
    Filed: February 2, 2015
    Publication date: December 1, 2016
    Applicant: HIROSHIMA UNIVERSITY
    Inventors: Tetsushi KOIDE, HoangAnh TUAN, Shigeto YOSHIDA, Tsubasa MISHIMA, Satoshi SHIGEMI, Toru TAMAKI, Tsubasa HIRAKAWA, Rie MIYAKI, Kouki SUGI
  • Publication number: 20160210520
    Abstract: In a symbol recognition device, each histogram computation module receives an image of each partial region of a recognition target region in a binarized image and computes a frequency distribution of pixels of a given color in each line or column in the partial region; each run length determination module receives an image of each partial region of the recognition target region and determines whether or not a line or column of pixels of the given color having a certain length is present in the partial region; a control module feeds pixel information of the partial regions, read by scanning the binarized image stored in the image memory, into the histogram computation modules and the run length determination modules; a determination module determines a symbol included in the binarized image based on computation results of the histogram computation modules and determination results of the run length determination modules.
    Type: Application
    Filed: March 29, 2016
    Publication date: July 21, 2016
    Inventors: Tetsushi KOIDE, Hoang Anh TUAN, Masaharu YAMAMOTO, Tsubasa MISHIMA
  • Patent number: 8937828
    Abstract: An associative memory that can reduce search errors is provided. An associative memory includes R distance/time conversion circuits DT1 to DTR. The R distance/time conversion circuits DT1 to DTR each include a NAND circuit 40 and N bit stages 41 to 4k. The N bit stages 41 to 4k delay a signal from the NAND circuit 40 by longer delay time as the distance between reference data and search data is greater and oscillate the signal. Among R oscillation signals output from the distance/time conversion circuits DT1 to DTR, the earliest changing oscillation signal is detected as an oscillation signal for the Winner row.
    Type: Grant
    Filed: May 8, 2012
    Date of Patent: January 20, 2015
    Assignee: Hiroshima University
    Inventors: Hans Juergen Mattausch, Tetsushi Koide, Masahiro Yasuda, Seiryu Sasaki
  • Patent number: 8587980
    Abstract: An associative memory capable of reducing erroneous searches is provided. A storage memory in the associative memory stores reference data. A comparator circuit receives externally applied search data and obtains the distance (for example, the Hamming distance) between the reference data and the search data. An oscillating circuit outputs a pulse signal with an oscillating frequency corresponding to the distance obtained by the comparator circuit. Similarly, the oscillating circuits output pulse signals with oscillating frequencies according to the distance between the reference data in corresponding storage circuits and the search data. A WTA circuit receives the pulse signals. Reference data stored in a storage circuit corresponding to an oscillating circuit that outputs a pulse signal with the highest frequency is determined as the most similar reference data (Winner) to the search data.
    Type: Grant
    Filed: September 24, 2010
    Date of Patent: November 19, 2013
    Assignee: Hiroshima University
    Inventors: Hans Juergen Mattausch, Tetsushi Koide, Tania Ansari, Wataru Imafuku, Akihiro Kaya
  • Publication number: 20130114322
    Abstract: An associative memory that can reduce search errors is provided. An associative memory includes R distance/time conversion circuits DT1 to DTR. The R distance/time conversion circuits DT1 to DTR each include a NAND circuit 40 and N bit stages 41 to 4k. The N bit stages 41 to 4k delay a signal from the NAND circuit 40 by longer delay time as the distance between reference data and search data is greater and oscillate the signal. Among R oscillation signals output from the distance/time conversion circuits DT1 to DTR, the earliest changing oscillation signal is detected as an oscillation signal for the Winner row.
    Type: Application
    Filed: May 8, 2012
    Publication date: May 9, 2013
    Applicant: HIROSHIMA UNIVERSITY
    Inventors: Hans Juergen MATTAUSCH, Tetsushi KOIDE, Masahiro YASUDA, Seiryu SASAKI
  • Patent number: 8331120
    Abstract: An offset removal circuit (10) includes a removal circuit (1) and a removal circuit (2). The removal circuit (1) digitally removes offset voltage from an input voltage Vin. The removal circuit (2) removes offset voltage, in an analog manner, from the voltage subjected to offset voltage removal by the removal circuit (1). Then, the removal circuit (2) outputs the voltage subjected to the offset voltage removal to a non-inverting input terminal of a differential amplifier (20).
    Type: Grant
    Filed: July 31, 2008
    Date of Patent: December 11, 2012
    Assignee: Hiroshima University
    Inventors: Hans Juergen Mattausch, Tetsushi Koide, Yuki Tanaka
  • Publication number: 20120188811
    Abstract: An associative memory capable of reducing erroneous searches is provided. A storage memory in the associative memory stores reference data. A comparator circuit receives externally applied search data and obtains the distance (for example, the Hamming distance) between the reference data and the search data. An oscillating circuit outputs a pulse signal with an oscillating frequency corresponding to the distance obtained by the comparator circuit. Similarly, the oscillating circuits output pulse signals with oscillating frequencies according to the distance between the reference data in corresponding storage circuits and the search data. A WTA circuit receives the pulse signals. Reference data stored in a storage circuit corresponding to an oscillating circuit that outputs a pulse signal with the highest frequency is determined as the most similar reference data (Winner) to the search data.
    Type: Application
    Filed: September 24, 2010
    Publication date: July 26, 2012
    Applicant: HIROSHIMA UNIVERSITY
    Inventors: Hans Juergen Mattausch, Tetsushi Koide, Tania Ansari, Wataru Imafuku, Akihiro Kaya
  • Patent number: 7957171
    Abstract: Associative memories capable of outputting multiple reference data close to search data are provided. A memory array compares each of the multiple reference data with the search data in parallel and generates multiple comparison current signals representing the result of the comparison. A WLA converts the multiple comparison current signals into voltages. During the first cycle, the WLA detects the lowest voltage among the voltages as Winner and detects the remaining voltages as Loser. After the second cycle, based on feedback signals, the WLA detects all the voltages other than a voltage detected as Winner during the last preceding cycle, and detects the lowest voltage among the detected voltages as Winner and detects the remaining detected voltages as Loser. The WLA repeats these operations k times.
    Type: Grant
    Filed: May 28, 2008
    Date of Patent: June 7, 2011
    Assignee: Hiroshima University
    Inventors: Md. Anwarul Abedin, Tetsushi Koide, Hans Juergen Mattausch, Yuki Tanaka
  • Patent number: 7881525
    Abstract: The present invention is directed to a pattern recognition system in which new reference data to be added is efficiently learned. In the pattern recognition system, there is performed the calculation of distances equivalent to similarities between input data of a pattern search target and a plurality of reference data, and based on input data of a fixed number of times corresponding to the reference data set as a recognized winner, a gravity center thereof is calculated to optimize the reference data. Furthermore, a threshold value is changed to enlarge/reduce recognition areas, whereby erroneous recognition is prevented and a recognition rate is improved.
    Type: Grant
    Filed: August 24, 2006
    Date of Patent: February 1, 2011
    Assignee: Hiroshima University
    Inventors: Hans Jurgen Mattausch, Tetsushi Koide, Yoshinori Shirakawa
  • Patent number: 7860328
    Abstract: A dividing unit divides respective symbol sequences of input data applied with zigzag scan and a run-length process into a plurality of subsets having similar frequencies of occurrence, depending on a difference in frequencies of occurrence. A table creating unit scans each subset and creates a Huffman coding table for each subset. A coding unit executes a process for performing Huffman coding on each subset by using the Huffman coding table created for the subset, for all of the subsets in the plurality of subsets.
    Type: Grant
    Filed: July 31, 2008
    Date of Patent: December 28, 2010
    Assignee: Hiroshima University
    Inventors: Hans Juergen Mattausch, Tetsushi Koide, Takeshi Kumaki, Masakatsu Ishizaki
  • Patent number: 7853075
    Abstract: A pixel-value detecting circuit (1) detects RGB values of each pixel of an input image and outputs the detected RGB values to a connection weight determining circuit (2). When both of two adjacent pixels have achromatic color, the connection weight determining circuit (2) determines a first connection weight, which is a connection weight between the two pixels, by using only the RGB values. When one of the two pixels has achromatic color, the connection weight determining circuit (2) determines, as a connection weight, a second connection weight that is smaller than the first connection weight, by using the RGB values and saturations. When both of the two pixels have chromatic color, the connection weight determining circuit (2) determines, as a connection weight, a third connection weight that is greater than or equal to the first connection weight, by using the RGB values and hues.
    Type: Grant
    Filed: July 31, 2008
    Date of Patent: December 14, 2010
    Assignee: Hiroshima University
    Inventors: Hans Juergen Mattausch, Tetsushi Koide, Kosuke Yamaoka
  • Publication number: 20100202178
    Abstract: An offset removal circuit (10) includes a removal circuit (1) and a removal circuit (2). The removal circuit (1) digitally removes offset voltage from an input voltage Vin. The removal circuit (2) removes offset voltage, in an analog manner, from the voltage subjected to offset voltage removal by the removal circuit (1). Then, the removal circuit (2) outputs the voltage subjected to the offset voltage removal to a non-inverting input terminal of a differential amplifier (20).
    Type: Application
    Filed: July 31, 2008
    Publication date: August 12, 2010
    Inventors: Hans Juergen Mattausch, Tetsushi Koide, Yuki Tanaka
  • Publication number: 20100202684
    Abstract: A pixel-value detecting circuit (1) detects RGB values of each pixel of an input image and outputs the detected RGB values to a connection weight determining circuit (2). When both of two adjacent pixels have achromatic color, the connection weight determining circuit (2) determines a first connection weight, which is a connection weight between the two pixels, by using only the RGB values. When one of the two pixels has achromatic color, the connection weight determining circuit (2) determines, as a connection weight, a second connection weight that is smaller than the first connection weight, by using the RGB values and saturations. When both of the two pixels have chromatic color, the connection weight determining circuit (2) determines, as a connection weight, a third connection weight that is greater than or equal to the first connection weight, by using the RGB values and hues.
    Type: Application
    Filed: July 31, 2008
    Publication date: August 12, 2010
    Inventors: Hans Juergen Mattausch, Tetsushi Koide, Kosuke Yamaoka
  • Publication number: 20100189351
    Abstract: A dividing unit divides respective symbol sequences of input data applied with zigzag scan and a run-length process into a plurality of subsets having similar frequencies of occurrence, depending on a difference in frequencies of occurrence. A table creating unit scans each subset and creates a Huffman coding table for each subset. A coding unit executes a process for performing Huffman coding on each subset by using the Huffman coding table created for the subset, for all of the subsets in the plurality of subsets.
    Type: Application
    Filed: July 31, 2008
    Publication date: July 29, 2010
    Inventors: Hans Juergen Mattausch, Tetsushi Koide, Takeshi Kumaki, Masakatsu Ishizaki
  • Publication number: 20100179976
    Abstract: A semiconductor device includes a decoder receiving first multiplier data of 3 bits indicating a multiplier to output a shift flag, an inversion flag, and an operation flag in accordance with Booth's algorithm, and a first partial product calculation unit receiving first multiplicand data of 2 bits indicating a multiplicand, a shift flag, an inversion flag, and an operation flag to select one of the higher order bit and lower order bit of the first multiplicand data based on the shift flag, invert or non-invert the selected bit based on the inversion flag, select one of the inverted or non-inverted data and data of a predetermined logic level based on the operation flag, and output the selected data as partial product data indicating the partial product of the first multiplier data and the first multiplicand data.
    Type: Application
    Filed: January 14, 2010
    Publication date: July 15, 2010
    Inventors: Masakatsu ISHIZAKI, Takeshi Kumaki, Masaharu Tagami, Yuta Imai, Tetsushi Koide, Hans Jürgen Mattausch, Takayuki Gyoten, Hideyuki Noda, Yoshihiro Okuno, Kazutami Arimoto