Patents by Inventor Tetsushi Koide
Tetsushi Koide has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 7746678Abstract: An amplifier circuit according to the present invention includes a plurality of input nodes receiving a plurality of input voltages (VI1 to VIR), a plurality of differential amplifiers provided corresponding to the plurality of input nodes, each having one input which receives a voltage of the corresponding input node, and a control circuit generating a control voltage (CONTROL) that follows a minimum voltage or a maximum voltage of the plurality of input voltages (VI1 to VIR) from outputs of the plurality of differential amplifiers and supplying the generated control voltage (CONTROL) as a common value to the other inputs of the plurality of differential amplifiers.Type: GrantFiled: February 22, 2008Date of Patent: June 29, 2010Assignee: Hiroshima UniversityInventors: Hans Juergen Mattausch, Tetsushi Koide, Yuki Tanaka, Md. Anwarul Abedin
-
Publication number: 20100085790Abstract: An amplifier circuit according to the present invention includes a plurality of input nodes receiving a plurality of input voltages (VI1 to VIR), a plurality of differential amplifiers provided corresponding to the plurality of input nodes, each having one input which receives a voltage of the corresponding input node, and a control circuit generating a control voltage (CONTROL) that follows a minimum voltage or a maximum voltage of the plurality of input voltages (VI1 to VIR) from outputs of the plurality of differential amplifiers and supplying the generated control voltage (CONTROL) as a common value to the other inputs of the plurality of differential amplifiers.Type: ApplicationFiled: February 22, 2008Publication date: April 8, 2010Inventors: Hans Juergen Mattausch, Tetsushi Koide, Yuki Tanaka, Md. Anwarul Abedin
-
Patent number: 7694077Abstract: A multi-port instruction/data integrated cache which is provided between a parallel processor and a main memory and stores therein a part of instructions and data stored in the main memory has a plurality of banks, and a plurality of ports including an instruction port unit consisting of at least one instruction port used to access an instruction from the parallel processor and a data port unit consisting of at least one data port used to access data from the parallel processor. Further, a data width which can be specified to the bank from the instruction port is set larger than a data width which can be specified to the bank from the data port.Type: GrantFiled: February 20, 2008Date of Patent: April 6, 2010Assignee: Semiconductor Technology Academic Research CenterInventors: Tetsuo Hironaka, Hans Jürgen Mattausch, Tetsushi Koide, Tai Hirakawa, Koh Johguchi
-
Patent number: 7599557Abstract: In a boundary active only scheme proposed by the present invention, only a cell in a boundary of region growth is brought into an active mode, and the other cells are brought into a standby mode. The respective cells perform state transition in parallel, and decision of the state transition performed for each clock cycle is not performed in a case where any of the three conditions that none of the adjacent cells is ignited, the cell itself is already ignited, and the cell already belongs to a certain divided region is satisfied. Therefore the number of simultaneously operating cells and that of coupling weight registers are minimized, and control is automatically executed to reduce power consumption.Type: GrantFiled: April 7, 2008Date of Patent: October 6, 2009Assignee: Hiroshima UniversityInventors: Tetsushi Koide, Hans Jurgen Mattausch, Takashi Morimoto, Youmei Harada
-
Patent number: 7561743Abstract: In an associative memory, when a reference data having the minimum distance with respect to an input data is detected as winner, it is determined whether or not a distance between the input data and winner is less than a threshold value. If the distance is less than the threshold value, it is determined that the reference data detected as winner matches with the input data, and then, a rank of the reference data is improved. If the distance is more than the threshold value, it is determined that the reference data is data different from the input data, and then, the input data is written as new reference data to the associative memory and replaces the reference data with the lowest rank. The upper positions of rank form as a long-term memory, and the lower positions thereof form as a short-term memory.Type: GrantFiled: December 20, 2004Date of Patent: July 14, 2009Assignee: Hiroshima UniversityInventors: Hans Jurgen Mattausch, Tetsushi Koide, Masahiro Mizokami
-
Publication number: 20090141531Abstract: Associative memories capable of outputting multiple reference data close to search data are provided. A memory array compares each of the multiple reference data with the search data in parallel and generates multiple comparison current signals representing the result of the comparison. A WLA converts the multiple comparison current signals into voltages. During the first cycle, the WLA detects the lowest voltage among the voltages as Winner and detects the remaining voltages as Loser. After the second cycle, based on feedback signals, the WLA detects all the voltages other than a voltage detected as Winner during the last preceding cycle, and detects the lowest voltage among the detected voltages as Winner and detects the remaining detected voltages as Loser. The WLA repeats these operations k times.Type: ApplicationFiled: May 28, 2008Publication date: June 4, 2009Inventors: Md. Anwarul Abedin, Tetsushi Koide, Hans Juergen Mattausch, Yuki Tanaka
-
Patent number: 7526127Abstract: In a boundary active only scheme proposed by the present invention, only a cell in a boundary of region growth is brought into an active mode, and the other cells are brought into a standby mode. The respective cells perform state transition in parallel, and decision of the state transition performed for each clock cycle is not performed in a case where any of the three conditions that none of the adjacent cells is ignited, the cell itself is already ignited, and the cell already belongs to a certain divided region is satisfied. Therefore the number of simultaneously operating cells and that of coupling weight registers are minimized, and control is automatically executed to reduce power consumption.Type: GrantFiled: August 11, 2004Date of Patent: April 28, 2009Assignee: Hiroshima University, a National University Corporation of JapanInventors: Tetsushi Koide, Hans Jurgen Mattausch, Takashi Morimoto, Youmei Harada
-
Publication number: 20080222360Abstract: A multi-port instruction/data integrated cache which is provided between a parallel processor and a main memory and stores therein a part of instructions and data stored in the main memory has a plurality of banks, and a plurality of ports including an instruction port unit consisting of at least one instruction port used to access an instruction from the parallel processor and a data port unit consisting of at least one data port used to access data from the parallel processor. Further, a data width which can be specified to the bank from the instruction port is set larger than a data width which can be specified to the bank from the data port.Type: ApplicationFiled: February 20, 2008Publication date: September 11, 2008Applicant: SEMICONDUCTOR TECHNOLOGY ACADEMIC RESEARCH CENTERInventors: Tetsuo Hironaka, Hans Jurgen Mattausch, Tetsushi Koide, Tai Hirakawa, Koh Johguchi
-
Publication number: 20080187223Abstract: In a boundary active only scheme proposed by the present invention, only a cell in a boundary of region growth is brought into an active mode, and the other cells are brought into a standby mode. The respective cells perform state transition in parallel, and decision of the state transition performed for each clock cycle is not performed in a case where any of the three conditions that none of the adjacent cells is ignited, the cell itself is already ignited, and the cell already belongs to a certain divided region is satisfied. Therefore the number of simultaneously operating cells and that of coupling weight registers are minimized, and control is automatically executed to reduce power consumption.Type: ApplicationFiled: April 7, 2008Publication date: August 7, 2008Applicant: HIROSHIMA University, A Nat'l Univ. Corp of JapanInventors: Tetsushi KOIDE, Hans Jurgen Mattausch, Takashi Morimoto, Youmei Harada
-
Publication number: 20080106469Abstract: The present invention provides a semiconductor device in which, in order to prevent wiring delay, an electromagnetic wave is radiated from a transmitting dipole antenna placed on a semiconductor chip and received with a receiving antenna placed in a circuit block included in another semiconductor chip, instead of long metal wires or via-hole interconnection.Type: ApplicationFiled: March 29, 2004Publication date: May 8, 2008Applicant: Japan Science and Technology AgencyInventors: Takamaro Kikkawa, Atsushi Iwata, Hideo Sunami, Hans Jurgen Mattausch, Shin Yokoyama, Kentaro Shibahara, Anri Nakajima, Tetsushi Koide, A.B.M. Harun-ur Rashid, Shinji Watanabe
-
Patent number: 7360024Abstract: A multi-port instruction/data integrated cache which is provided between a parallel processor and a main memory and stores therein a part of instructions and data stored in the main memory has a plurality of banks, and a plurality of ports including an instruction port unit consisting of at least one instruction port used to access an instruction from the parallel processor and a data port unit consisting of at least one data port used to access data from the parallel processor. Further, a data width which can be specified to the bank from the instruction port is set larger than a data width which can be specified to the bank from the data port.Type: GrantFiled: October 15, 2003Date of Patent: April 15, 2008Assignee: Semiconductor Technology Academic Research CenterInventors: Tetsuo Hironaka, Hans Jürgen Mattausch, Tetsushi Koide, Tai Hirakawa, Koh Johguchi
-
Patent number: 7298899Abstract: Cells i corresponding to pixels are initialized into a non-excitation state, to calculate coupling weights Wik between the eight cells k adjacent to the cells i, thereby determining leader cells pi=1 based on calculation results. Next, one leader cell yet to be excited is selected as a self-excitable cell. The selected cell is put into the excitation state, the excitable cells are selected based on the coupling weights between the adjacent cells, and the selected cells are put into the excitation state. These operations are repeated until no excitable cell is detected any more and, if there no excitable cell is detected any more, inhibition processing is performed, thereby completing image segmentation of one region. These operations are repeated until there is no non-excited and non-inhibited leader cell any more, thereby pinpointing regions belonging to the same category from an input image and identifying them as an image segmentation regions.Type: GrantFiled: May 27, 2003Date of Patent: November 20, 2007Assignee: President of Hiroshima UniversityInventors: Tetsushi Koide, Hans Juergen Mattausch, Takashi Morimoto, Youmei Harada
-
Patent number: 7203382Abstract: A plurality of reference words based on a second distance index that allows coding of a first distance index are registered in an associative memory core in advance. In a first pipeline stage, a retrieved word having a predetermined number of bits is extracted from input data in a predetermined clock cycle, and the retrieved word is coded with the second distance index and output to the core. In a second pipeline stage, the core searches for a reference word inhabiting the largest similarity with respect to the retrieved word (winner) obtained in the previous clock cycle. In a third pipeline stage, the core output result in the previous clock cycle is analyzed, one winner is determined on the basis of a specific priority, and an address indicating the location of the winner and the distance between the input data and the winner are coded and output.Type: GrantFiled: June 4, 2003Date of Patent: April 10, 2007Assignee: President of Hiroshima UniversityInventors: Hans Juergen Mattausch, Tetsushi Koide
-
Publication number: 20070003135Abstract: The present invention is directed to a pattern recognition system in which new reference data to be added is efficiently learned. In the pattern recognition system, there is performed the calculation of distances equivalent to similarities between input data of a pattern search target and a plurality of reference data, and based on input data of a fixed number of times corresponding to the reference data set as a recognized winner, a gravity center thereof is calculated to optimize the reference data. Furthermore, a threshold value is changed to enlarge/reduce recognition areas, whereby erroneous recognition is prevented and a recognition rate is improved.Type: ApplicationFiled: August 24, 2006Publication date: January 4, 2007Inventors: Hans Mattausch, Tetsushi Koide, Yoshinori Shirakawa
-
Patent number: 7117291Abstract: In a synchronous multi-port bank memory, registers/buffers receive a read/write signal and an address signal from each of external ports, receive and send a data signal to and from each of the external ports, and receive and send a port block signal. An access conflict management circuit receives the address signals from the registers and buffers and generates the port block signal when an access conflict to the bank occurs. A switching network receives the read/write signal and the address signal from the registers/buffers and generates a bank selection signal when no port block signal is received, so as to activate the selected bank. Thus, memory access cycle time is shortened. A synchronous 1-port bank memory is also constructed similarly.Type: GrantFiled: February 27, 2004Date of Patent: October 3, 2006Assignee: Semiconductor Technology Academic Research CenterInventors: Hans Jurgen Mattausch, Tetsushi Koide, Tetsuo Hironaka, Hiroshi Uchida, Koh Johguchi, Zhaomin Zhu
-
Patent number: 7113416Abstract: In the present invention, focusing on the point that the number of transistors can be reduced to about ? of that in a prior art due to an absolute-value-of-difference calculating circuit for an associative memory being configured of an addition circuit and a bit inversion circuit. The absolute-value-of-difference calculating circuit is built in a fully-parallel type associative memory as a unit comparison circuit, and all of the outputs of the absolute-value-of-difference calculating circuits for which the number of comparisons thereof are prepared are input to weight comparison circuits, whereby the calculation of the Manhattan distance between the search data and the reference data is carried out. In accordance with the configuration, because a Manhattan distance calculating circuit can be realized by a fewer number of transistors and with a small area, an associative memory apparatus as well can be realized at a low power consumption and with a small area.Type: GrantFiled: August 11, 2004Date of Patent: September 26, 2006Assignee: Hiroshima UniversityInventors: Tetsushi Koide, Hans Jurgen Mattausch, Yuji Yano
-
Publication number: 20050162878Abstract: In the present invention, focusing on the point that the number of transistors can be reduced to about ? of that in a prior art due to an absolute-value-of-difference calculating circuit for an associative memory being configured of an addition circuit and a bit inversion circuit. The absolute-value-of-difference calculating circuit is built in a fully-parallel type associative memory as a unit comparison circuit, and all of the outputs of the absolute-value-of-difference calculating circuits for which the number of comparisons thereof are prepared are input to weight comparison circuits, whereby the calculation of the Manhattan distance between the search data and the reference data is carried out. In accordance with the configuration, because a Manhattan distance calculating circuit can be realized by a fewer number of transistors and with a small area, an associative memory apparatus as well can be realized at a low power consumption and with a small area.Type: ApplicationFiled: August 11, 2004Publication date: July 28, 2005Inventors: Tetsushi Koide, Hans Mattausch, Yuji Yano
-
Publication number: 20050154726Abstract: In an associative memory, when a reference data having the minimum distance with respect to an input data is detected as winner, it is determined whether or not a distance between the input data and winner is less than a threshold value. If the distance is less than the threshold value, it is determined that the reference data detected as winner matches with the input data, and then, a rank of the reference data is improved. If the distance is more than the threshold value, it is determined that the reference data is data different from the input data, and then, the input data is written as new reference data to the associative memory and replaces the reference data with the lowest rank. The upper positions of rank form as a long-term memory, and the lower positions thereof form as a short-term memory.Type: ApplicationFiled: December 20, 2004Publication date: July 14, 2005Inventors: Hans Mattausch, Tetsushi Koide, Masahiro Mizokami
-
Publication number: 20050125594Abstract: In a synchronous multi-port bank memory, registers/buffers receive a read/write signal and an address signal from each of external ports, receive and send a data signal to and from each of the external ports, and receive and send a port block signal. An access conflict management circuit receives the address signals from the registers and buffers and generates the port block signal when an access conflict to the bank occurs. A switching network receives the read/write signal and the address signal from the registers/buffers and generates a bank selection signal when no port block signal is received, so as to activate the selected bank. Thus, memory access cycle time is shortened. A synchronous 1-port bank memory is also constructed similarly.Type: ApplicationFiled: February 27, 2004Publication date: June 9, 2005Inventors: Hans Mattausch, Tetsushi Koide, Tetsuo Hironaka, Hiroshi Uchida, Koh Johguchi, Zhaomin Zhu
-
Publication number: 20050058345Abstract: In a boundary active only scheme proposed by the present invention, only a cell in a boundary of region growth is brought into an active mode, and the other cells are brought into a standby mode. The respective cells perform state transition in parallel, and decision of the state transition performed for each clock cycle is not performed in a case where any of the three conditions that none of the adjacent cells is ignited, the cell itself is already ignited, and the cell already belongs to a certain divided region is satisfied. Therefore the number of simultaneously operating cells and that of coupling weight registers are minimized, and control is automatically executed to reduce power consumption.Type: ApplicationFiled: August 11, 2004Publication date: March 17, 2005Inventors: Tetsushi Koide, Hans Mattausch, Takashi Morimoto, Youmei Harada