Abstract: A self-adjusting winner lineup amplifier comprising signal control sections which level-control comparison signals (Ci) from word weighted comparators of a memory area, a self-adjusting distance amplifying section corresponding to the respective rows in the memory area which outputs the level-controlled comparison signals (Ci) as distance amplified signals (LAi), a feedback generating section which inputs a self-adjusting voltage (Fa) common to the distance amplifying sections, and a voltage follower which converts its input voltage (min{Ci}; a minimum value of Ci) into a feedback voltage (F) to supply the feedback voltage (F) in parallel and with strong driving current to the signal control sections, wherein amplification characteristics of the distance amplifying section are self-adjusted by a comparison signal (Cwin) of a winner row, and the signal control sections lead the comparison signal (Cwin) into the range of a maximum gain area of the distance amplifying section.

Abstract: A multi-port instruction/data integrated cache which is provided between a parallel processor and a main memory and stores therein a part of instructions and data stored in the main memory has a plurality of banks, and a plurality of ports including an instruction port unit consisting of at least one instruction port used to access an instruction from the parallel processor and a data port unit consisting of at least one data port used to access data from the parallel processor. Further, a data width which can be specified to the bank from the instruction port is set larger than a data width which can be specified to the bank from the data port.

Abstract: A plurality of reference words based on a second distance index that allows coding of a first distance index are registered in an associative memory core in advance. In a first pipeline stage, a retrieved word having a predetermined number of bits is extracted from input data in a predetermined clock cycle, and the retrieved word is coded with the second distance index and output to the core. In a second pipeline stage, the core searches for a reference word inhabiting the largest similarity with respect to the retrieved word (winner) obtained in the previous clock cycle. In a third pipeline stage, the core output result in the previous clock cycle is analyzed, one winner is determined on the basis of a specific priority, and an address indicating the location of the winner and the distance between the input data and the winner are coded and output.

Abstract: A self-adjusting winner lineup amplifier comprising signal control sections which level-control comparison signals (Ci) from word weighted comparators of a memory area, a self-adjusting distance amplifying section corresponding to the respective rows in the memory area which outputs the level-controlled comparison signals (Ci) as distance amplified signals (LAi), a feedback generating section which inputs a self-adjusting voltage (Fa) common to the distance amplifying sections, and a voltage follower which converts its input voltage (min{Ci}; a minimum value of Ci) into a feedback voltage (F) to supply the feedback voltage (F) in parallel and with strong driving current to the signal control sections, wherein amplification characteristics of the distance amplifying section are self-adjusted by a comparison signal (Cwin) of a winner row, and the signal control sections lead the comparison signal (Cwin) into the range of a maximum gain area of the distance amplifying section.

Abstract: Cells i corresponding to pixels are initialized into a non-excitation state, to calculate coupling weights Wik between the eight cells k adjacent to the cells i, thereby determining leader cells pi=1 based on calculation results. Next, one leader cell yet to be excited is selected as a self-excitable cell. The selected cell is put into the excitation state, the excitable cells are selected based on the coupling weights between the adjacent cells, and the selected cells are put into the excitation state. These operations are repeated until no excitable cell is detected any more and, if there no excitable cell is detected any more, inhibition processing is performed, thereby completing image segmentation of one region. These operations are repeated until there is no non-excited and non-inhibited leader cell any more, thereby pinpointing regions belonging to the same category from an input image and identifying them as an image segmentation regions.