Patents by Inventor Tetsuya Hayashida

Tetsuya Hayashida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12092970
    Abstract: An image forming apparatus, to which a cartridge including a developer accommodating portion for accommodating a developer is detachably mountable, includes an image bearing member, an exposure unit configured to expose the image bearing member to light to form an electrostatic latent image on the image bearing member, a light receiving sensor provided in the cartridge and configured to receive the light emitted from the exposure unit, and a controller configured to detect vibration of the cartridge from a light reception value of the light received by the light receiving sensor. In a case in which the cartridge is removed from the image forming apparatus, the light receiving sensor is removed from the image forming apparatus together with the cartridge.
    Type: Grant
    Filed: March 30, 2022
    Date of Patent: September 17, 2024
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Kohei Matsuda, Junko Hirata, Kazunori Hashimoto, Yasushi Katsuta, Makoto Hayashida, Yasunori Toriyama, Hiroomi Matsuzaki, Fumito Nonaka, Kazuki Matsumoto, Tetsuya Nishiguchi
  • Patent number: 8820547
    Abstract: Provided is a movable rack unit for taking in and out a storage object with respect to a storage space. The movable rack unit includes a guide part including a track member linearly laid inside the storage space and along a depth direction of the storage space and a moving body that moves along the track member. A support member is rotatably borne on the moving body, and the support member supports the storage object within the storage space. Further, this unit includes a rotation guiding part, and the rotation guiding part changes the attitude of the support member in accordance with the position of the moving body with respect to the track member. When the moving member reaches an opening portion side of the storage space, the rotation guiding part rotates the support member so that merely the support member is set outside the storage space.
    Type: Grant
    Filed: August 7, 2013
    Date of Patent: September 2, 2014
    Assignee: THK Co., Ltd.
    Inventors: Tetsuya Hayashida, Eiji Hosaka
  • Publication number: 20140048504
    Abstract: Provided is a movable rack unit for taking in and out a storage object with respect to a storage space. The movable rack unit includes a guide part including a track member linearly laid inside the storage space and along a depth direction of the storage space and a moving body that moves along the track member. A support member is rotatably borne on the moving body, and the support member supports the storage object within the storage space. Further, this unit includes a rotation guiding part, and the rotation guiding part changes the attitude of the support member in accordance with the position of the moving body with respect to the track member. When the moving member reaches an opening portion side of the storage space, the rotation guiding part rotates the support member so that merely the support member is set outside the storage space.
    Type: Application
    Filed: August 7, 2013
    Publication date: February 20, 2014
    Applicant: THK CO., LTD.
    Inventors: Tetsuya Hayashida, Eiji Hosaka
  • Patent number: 6953709
    Abstract: A semiconductor device having area array bump electrodes suitable for flip chip packaging is disclosed. A semiconductor chip with wire bonding electrodes arranged along peripheral edges thereof is provided, then gold wire bump electrodes are formed over the wire bonding electrodes, and thereafter a wiring tape substrate is superimposed on the semiconductor chip and is bonded thereto with an adhesive. On a back surface of the wiring tape substrate are formed wiring connections correspondingly to the electrodes. Further, at the time of bonding with use of the adhesive, convex tips of the gold wire bump electrodes formed respectively on the electrodes of the semiconductor chip pierce through the adhesive to connect the gold wire bump electrodes and the connections electrically with each other. On a surface of the wiring tape substrate are formed area array bump electrodes, whose pitch is larger than the pitch of the electrodes formed on the semiconductor chip.
    Type: Grant
    Filed: April 18, 2002
    Date of Patent: October 11, 2005
    Assignees: Renesas Technology Corp., Renesas Northern Japan Semiconductor, Inc.
    Inventor: Tetsuya Hayashida
  • Patent number: 6787442
    Abstract: By a solder bump, a CSP is bonded to a first electrode of the module substrate of a multi-chip module. For this solder bump, a solder added with an alkaline earth metal such as Ba, Be, Ca or Mg is used. Accordingly, upon solder reflow, phosphorous (P) reacts with the alkaline earth metal, thereby forming a P compound. Owing to dispersion of this P compound inside of the solder bump, no P concentrated layer is formed on the Ni film, making it possible to prevent peeling of the solder bump from the first electrode upon solder reflow. Thus, the present invention makes it possible to improve the solder bonding property.
    Type: Grant
    Filed: February 5, 2003
    Date of Patent: September 7, 2004
    Assignees: Renesas Technology Corp., Hitachi Hokkai Semiconductor, Ltd.
    Inventor: Tetsuya Hayashida
  • Publication number: 20040171193
    Abstract: A semiconductor device having area array bump electrodes suitable for flip chip packaging is disclosed. A semiconductor chip with wire bonding electrodes arranged along peripheral edges thereof is provided, then gold wire bump electrodes are formed over the wire bonding electrodes, and thereafter a wiring tape substrate is superimposed on the semiconductor chip and is bonded thereto with an adhesive. On a back surface of the wiring tape substrate are formed wiring connections correspondingly to the electrodes. Further, at the time of bonding with use of the adhesive, convex tips of the gold wire bump electrodes formed respectively on the electrodes of the semiconductor chip pierce through the adhesive to connect the gold wire bump electrodes and the connections electrically with each other. On a surface of the wiring tape substrate are formed area array bump electrodes, whose pitch is larger than the pitch of the electrodes formed on the semiconductor chip.
    Type: Application
    Filed: January 20, 2004
    Publication date: September 2, 2004
    Inventor: Tetsuya Hayashida
  • Patent number: 6780677
    Abstract: An electronic device comprising a semiconductor chip which is fixed to the mounting face of a wiring board through an adhesive and in which external terminals are electrically connected with electrode pads of the wiring board through bump electrodes. Recesses are formed in the electrode pads, and in the recesses the electrode pads and the bump electrodes are connected. The electrode pads are formed over the surface of a soft layer, and the recesses are formed by elastic deformation of the electrode pads and the soft layer.
    Type: Grant
    Filed: August 21, 2002
    Date of Patent: August 24, 2004
    Assignees: Hitachi, Ltd., Hitachi Hokkai Semiconductor, Ltd.
    Inventors: Satoshi Imasu, Ikuo Yoshida, Tetsuya Hayashida, Akira Yamagiwa, Shinobu Takeura
  • Patent number: 6781234
    Abstract: By a solder bump, a CSP is bonded to a first electrode of the module substrate of a multi-chip module. For this solder bump, a solder added with an alkaline earth metal such as Ba, Be, Ca or Mg is used. Accordingly, upon solder reflow, phosphorous (P) reacts with the alkaline earth metal, thereby forming a P compound. Owing to dispersion of this P compound inside of the solder bump, no P concentrated layer is formed on the Ni film, making it possible to prevent peeling of the solder bump from the first electrode upon solder reflow. Thus, the present invention makes it possible to improve the solder bonding property.
    Type: Grant
    Filed: June 19, 2002
    Date of Patent: August 24, 2004
    Assignees: Renesas Technology Corp., Hitachi Hokkai Semiconductor, Ltd.
    Inventor: Tetsuya Hayashida
  • Patent number: 6767767
    Abstract: A semiconductor device manufacturing method is disclosed which can reduce the cost of manufacturing an MAP type semiconductor device. According to this method, a substrate with semiconductor chips mounted at predetermined intervals in a matrix shape on a main surface thereof is clamped between a lower mold and an upper mold of a molding die, an insulating resin is injected through gates into a cavity formed on the main surface side of the substrate, air present within the cavity is allowed to escape from air vents, to form a block molding package which covers the semiconductor chips, thereafter bump electrodes are formed on a back surface of the substrate, and then the block molding package and the substrate are cut longitudinally and transversely to fabricate plural semiconductor devices. The air vents are formed by grooves provided in the substrate.
    Type: Grant
    Filed: July 16, 2002
    Date of Patent: July 27, 2004
    Assignees: Renesas Technology Corp., Hitachi Hokkai Semiconductor, Ltd.
    Inventors: Tetsuya Hayashida, Norihiko Kasai
  • Patent number: 6737741
    Abstract: An electronic device comprising a semiconductor chip which is fixed to the mounting face of a wiring board through an adhesive and in which external terminals are electrically connected with electrode pads of the wiring board through bump electrodes. Recesses are formed in the electrode pads, and in the recesses the electrode pads and the bump electrodes are connected. The electrode pads are formed over the surface of a soft layer, and the recesses are formed by elastic deformation of the electrode pads and the soft layer.
    Type: Grant
    Filed: August 21, 2002
    Date of Patent: May 18, 2004
    Assignees: Hitachi, Ltd., Hitachi Hokkai Semiconductor, Ltd.
    Inventors: Satoshi Imasu, Ikuo Yoshida, Tetsuya Hayashida, Akira Yamagiwa, Shinobu Takeura
  • Publication number: 20030119298
    Abstract: By a solder bump, a CSP is bonded to a first electrode of the module substrate of a multi-chip module. For this solder bump, a solder added with an alkaline earth metal such as Ba, Be, Ca or Mg is used. Accordingly, upon solder reflow, phosphorous (P) reacts with the alkaline earth metal, thereby forming a P compound. Owing to dispersion of this P compound inside of the solder bump, no P concentrated layer is formed on the Ni film, making it possible to prevent peeling of the solder bump from the first electrode upon solder reflow. Thus, the present invention makes it possible to improve the solder bonding property.
    Type: Application
    Filed: February 5, 2003
    Publication date: June 26, 2003
    Applicant: Hitachi, Ltd.
    Inventor: Tetsuya Hayashida
  • Publication number: 20030045030
    Abstract: A semiconductor device manufacturing method is disclosed which can reduce the cost of manufacturing an MAP type semiconductor device. According to this method, a substrate with semiconductor chips mounted at predetermined intervals in a matrix shape on a main surface thereof is clamped between a lower mold and an upper mold of a molding die, an insulating resin is injected through gates into a cavity formed on the main surface side of the substrate, air present within the cavity is allowed to escape from air vents, to form a block molding package which covers the semiconductor chips, thereafter bump electrodes are formed on a back surface of the substrate, and then the block molding package and the substrate are cut longitudinally and transversely to fabricate plural semiconductor devices. The air vents are formed by grooves provided in the substrate.
    Type: Application
    Filed: July 16, 2002
    Publication date: March 6, 2003
    Applicant: Hitachi, Ltd.
    Inventors: Tetsuya Hayashida, Norihiko Kasai
  • Publication number: 20030022479
    Abstract: By a solder bump, a CSP is bonded to a first electrode of the module substrate of a multi-chip module. For this solder bump, a solder added with an alkaline earth metal such as Ba, Be, Ca or Mg is used. Accordingly, upon solder reflow, phosphorous (P) reacts with the alkaline earth metal, thereby forming a P compound. Owing to dispersion of this P compound inside of the solder bump, no P concentrated layer is formed on the Ni film, making it possible to prevent peeling of the solder bump from the first electrode upon solder reflow. Thus, the present invention makes it possible to improve the solder bonding property.
    Type: Application
    Filed: June 19, 2002
    Publication date: January 30, 2003
    Applicant: Hitachi, Ltd.
    Inventor: Tetsuya Hayashida
  • Publication number: 20020195718
    Abstract: An electronic device comprising a semiconductor chip which is fixed to the mounting face of a wiring board through an adhesive and in which external terminals are electrically connected with electrode pads of the wiring board through bump electrodes. Recesses are formed in the electrode pads, and in the recesses the electrode pads and the bump electrodes are connected. The electrode pads are formed over the surface of a soft layer, and the recesses are formed by elastic deformation of the electrode pads and the soft layer.
    Type: Application
    Filed: August 21, 2002
    Publication date: December 26, 2002
    Applicant: HITACHI, LTD.
    Inventors: Satoshi Imasu, Ikuo Yoshida, Tetsuya Hayashida, Akira Yamagiwa, Shinobu Takeura
  • Publication number: 20020192865
    Abstract: An electronic device comprising a semiconductor chip which is fixed to the mounting face of a wiring board through an adhesive and in which external terminals are electrically connected with electrode pads of the wiring board through bump electrodes. Recesses are formed in the electrode pads, and in the recesses the electrode pads and the bump electrodes are connected. The electrode pads are formed over the surface of a soft layer, and the recesses are formed by elastic deformation of the electrode pads and the soft layer.
    Type: Application
    Filed: August 21, 2002
    Publication date: December 19, 2002
    Applicant: HITACHI, LTD. and HITACHI HOKKAI SEMICONDUCTOR, LTD.
    Inventors: Satoshi Imasu, Ikuo Yoshida, Tetsuya Hayashida, Akira Yamagiwa, Shinobu Takeura
  • Patent number: 6471115
    Abstract: The present invention is a process for manufacturing an electronic circuit device by applying a solder material to electronic parts or electrodes on a printed circuit board; the process comprising the steps of removing an initial surface oxide film and an organic contaminant film from the surfaces of the solder material and electrode, covering the solder material and an area to which solder is to be applied which is comprised of the electrode, with a liquid vaporizing up after the bonding is completed in the step of heat-melting the solder material, to thereby prevent reoxidation of the joining area surface, and heat-melting the solder material, to carry out solder bonding without using any flux.
    Type: Grant
    Filed: June 2, 2000
    Date of Patent: October 29, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Masahito Ijuin, Toru Nishikawa, Ryohei Sato, Mitsugu Shirai, Yuzo Taniguchi, Kosuke Inoue, Masahide Harada, Tetsuya Hayashida
  • Patent number: 6461896
    Abstract: An electronic device comprising a semiconductor chip which is fixed to the mounting face of a wiring board through an adhesive and in which external terminals are electrically connected with electrode pads of the wiring board through bump electrodes. Recesses are formed in the electrode pads, and in the recesses the electrode pads and the bump electrodes are connected. The electrode pads are formed over the surface of a soft layer, and the recesses are formed by elastic deformation of the electrode pads and the soft layer.
    Type: Grant
    Filed: May 5, 2000
    Date of Patent: October 8, 2002
    Assignees: Hitachi, Ltd., Hitachi Hokkai Semiconductor, Ltd.
    Inventors: Satoshi Imasu, Ikuo Yoshida, Tetsuya Hayashida, Akira Yamagiwa, Shinobu Takeura
  • Patent number: 6380621
    Abstract: An electrically reliable heat radiating package provided with ball grid array (BGA) structure and a method of manufacturing the package are disclosed. In the concrete, a semiconductor chip is mounted on one surface of a ceramic wiring board via a first soldered bump electrode and resin is filled in a gap area between the one surface of the wiring board and the principal surface of the semiconductor chip. A heat diffusing plate formed in larger plane size than that of the semiconductor chip by aluminum nitride is arranged on the rear surface opposite to the principal surface of the semiconductor chip and soldered. Further, a radiating fin made of aluminum is provided on the heat diffusing plate and stuck via silicone rubber in which thermally conductive filler is included.
    Type: Grant
    Filed: April 5, 2000
    Date of Patent: April 30, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Hideko Ando, Hiroshi Kikuchi, Toshihiko Sato, Tetsuya Hayashida
  • Publication number: 20010002162
    Abstract: An electronic device comprising a semiconductor chip which is fixed to the mounting face of a wiring board through an adhesive and in which external terminals are electrically connected with electrode pads of the wiring board through bump electrodes. Recesses are formed in the electrode pads, and in the recesses the electrode pads and the bump electrodes are connected. The electrode pads are formed over the surface of a soft layer, and the recesses are formed by elastic deformation of the electrode pads and the soft layer.
    Type: Application
    Filed: January 26, 2001
    Publication date: May 31, 2001
    Applicant: Hitachi, Ltd.
    Inventors: Satoshi Imasu, Ikuo Yoshida, Tetsuya Hayashida, Akira Yamagiwa, Shinobu Takeura
  • Publication number: 20010002163
    Abstract: An electronic device comprising a semiconductor chip which is fixed to the mounting face of a wiring board through an adhesive and in which external terminals are electrically connected with electrode pads of the wiring board through bump electrodes. Recesses are formed in the electrode pads, and in the recesses the electrode pads and the bump electrodes are connected. The electrode pads are formed over the surface of a soft layer, and the recesses are formed by elastic deformation of the electrode pads and the soft layer.
    Type: Application
    Filed: January 26, 2001
    Publication date: May 31, 2001
    Applicant: Hitachi, Ltd.
    Inventors: Satoshi Imasu, Ikuo Yoshida, Tetsuya Hayashida, Akira Yamagiwa, Shinobu Takeura