Patents by Inventor Tetsuya Iida

Tetsuya Iida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190072717
    Abstract: To provide a semiconductor device including a low-loss optical waveguide. The optical waveguide included in the semiconductor device has a core layer covered with first and second clad layers having respectively different refractive indices. A portion of the core layer is covered at a first ratio, that is, a ratio of the first clad layer to the second clad layer and at the same time, a second ratio, that is, a ratio of the second clad layer to the first clad layer. At this time, the first ratio and the second ratio are each a finite value more than 0.
    Type: Application
    Filed: July 16, 2018
    Publication date: March 7, 2019
    Inventors: Tetsuya IIDA, Yasutaka NAKASHIBA
  • Patent number: 10204987
    Abstract: In a semiconductor device including a super junction structure that p-type columns and n-type columns are periodically arranged, a depth of a p-type column region in a cell region that a semiconductor element is formed is made shallower than a depth of a p-type column region in an intermediate region which surrounds the cell region. Thereby, a breakdown voltage of the cell region becomes lower than a breakdown voltage of the intermediate region. An avalanche breakdown phenomenon is caused to occur preferentially in the cell region in which even when an avalanche current is generated, the current is dispersed and smoothly flows. Thereby, it is possible to avoid local current constriction and breakage incidental thereto and consequently it becomes possible to improve avalanche resistance (an avalanche current amount with which a semiconductor device comes to be broken).
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: February 12, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Yuya Abiko, Satoshi Eguchi, Akio Ichimura, Natsuo Yamaguchi, Tetsuya Iida
  • Patent number: 10197822
    Abstract: To reduce a production cost of a semiconductor device and provide a semiconductor device having improved characteristics. A grating coupler has a plurality of projections separated from each other in an optical waveguide direction and a slab portion formed between any two of the projections adjacent to each other and formed integrally with them; a MOS optical modulator has a projection extending in the optical waveguide direction and slab portions formed on both sides of the projection, respectively, and formed integrally therewith. The projection of the grating coupler and the MOS optical modulator is formed of a first semiconductor layer, a second insulating layer, and a second semiconductor layer stacked successively on a first insulating layer, while the grating coupler and the MOS optical modulator each have a slab portion formed of the first semiconductor layer.
    Type: Grant
    Filed: January 24, 2018
    Date of Patent: February 5, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Shinichi Kuwabara, Yasutaka Nakashiba, Tetsuya Iida, Shinichi Watanuki
  • Publication number: 20190029172
    Abstract: A mower includes including: a mower deck housing a plurality of cutting blades; cutting blade shafts individually supporting the cutting blades; a driven pulley fixed to the cutting blade shafts; a gearbox supported on an upper surface of the mower deck and configured to decelerate a driving force from an engine; a driving pulley fixed to an output shaft of the gearbox; and a belt wound around the driving pulley and the driven pulley, and the gearbox is pivotable upward about an end of the driving pulley around which the belt is wound.
    Type: Application
    Filed: January 20, 2016
    Publication date: January 31, 2019
    Applicant: Yanmar Co., Ltd.
    Inventor: Tetsuya IIDA
  • Publication number: 20190010863
    Abstract: A control device is provided capable of reliably preventing occurrence of a surging state by judging a possibility of the surging state in a relatively easy manner and promptly executing a surging state avoidance control. When a supercharging pressure decreasing state in which a target supercharging pressure decreases is detected, an operating speed of a wastegate valve is determined based on a detected engine rotational speed. That is, by lowering the operating speed as the engine rotational speed lowers, reduction in flow rate of the air passing through a compressor is prevented, and the occurrence of the surging state is reliably prevented. By lowering the operating speed instead of changing a target opening degree of the wastegate valve, a maximum opening degree of the wastegate valve can be suppressed, and responsiveness in the case where an acceleration request is made immediately after deceleration of an engine can be improved.
    Type: Application
    Filed: June 20, 2018
    Publication date: January 10, 2019
    Applicant: Honda Motor Co.,Ltd.
    Inventors: Yuichi MASUKAKE, Tetsuya IIDA, Yujiro TSUTSUMI, Ayumu HORIBA
  • Publication number: 20190004342
    Abstract: In an optical waveguide supplied with electricity by using a heater, miniaturization of the device is achieved by enhancing heat dissipation efficiency and heat resistance. In a modulator including an optical waveguide formed on an insulating film, a first interlayer insulating film that covers the optical waveguide, a heater formed on the first interlayer insulating film, and a second interlayer insulating film that covers the heater, a heat conducting portion adjacent to the optical waveguide and the heater and penetrating the first and second interlayer insulating films is formed.
    Type: Application
    Filed: May 11, 2018
    Publication date: January 3, 2019
    Inventors: Tetsuya IIDA, Yasutaka NAKASHIBA, Shinichi KUWABARA
  • Patent number: 10170865
    Abstract: The electric shielded wire connection structure includes: a lower side case that accommodates a rotary electric machine; an upper side case that is positioned immediately above, and facing, the lower side case and accommodates an inverter; a plurality of electric wires that is arranged in a state where one end thereof is connected to a lower side terminal block immediately under the upper side case, the other end thereof is connected to an upper side terminal block at a wall surface side end part of the upper side case, and the plurality of electric wires is bent from the position immediately under the upper side case so as to face the wall surface; and a braided shielding member that shields the plurality of electric wires and is arranged for the plurality of electric wires only at the side opposite to the surface facing the upper side case.
    Type: Grant
    Filed: October 16, 2015
    Date of Patent: January 1, 2019
    Assignees: TOYOTA JIDOSHA KABUSHIKI KAISHA, SUMITOMO WIRING SYSTEMS, LTD., AUTONETWORKS TECHNOLOGIES, LTD., Sumitomo Electric Industries, Ltd.
    Inventors: Yasuhiro Makido, Yousuke Kurono, Haruki Kusamaki, Tetsuya Iida, Junpei Nakamoto, Takuya Tate, Hiroyuki Matsuoka, Kouji Fukumoto, Daisuke Hashimoto, Toshiya Hirooka
  • Publication number: 20180366409
    Abstract: A compact semiconductor device with an isolator. The semiconductor device includes two chips, namely a first semiconductor chip and a second semiconductor chip which are stacked with the main surfaces of the semiconductor chips partially facing each other. A first coil and a second coil which are formed in the first semiconductor chip and the second semiconductor chip respectively are arranged to face each other so as to be magnetically coupled during operation of the semiconductor device. The pair of first and second coils make up an isolator. The first coil is arranged in a manner to overlap part of the circuit region of the first semiconductor chip in plan view and the second coil is arranged in a manner to overlap part of the circuit region of the second semiconductor chip in plan view.
    Type: Application
    Filed: April 16, 2018
    Publication date: December 20, 2018
    Inventors: Shinichi KUWABARA, Tetsuya IIDA, Yasutaka NAKASHIBA
  • Publication number: 20180342031
    Abstract: A picking assistant system includes an article shelf in which articles are stocked, a projector displaying an instruction to a worker in a display region defined on the article shelf, and a processor. The processor detects a motion of a movable member which constitutes the article shelf and is configured to move when the article is taken out from the article shelf, and detects an operational error of the worker based on the detected motion of the movable member.
    Type: Application
    Filed: September 12, 2016
    Publication date: November 29, 2018
    Applicant: AIOI SYSTEMS CO., LTD.
    Inventors: Kiyoshi TADA, Takamichi YOSHIKAWA, Takeshi SATO, Tetsuya IIDA
  • Patent number: 10141397
    Abstract: A super junction structure having a high aspect ratio is formed. An epitaxial layer is dividedly formed in layers using the trench fill process, and when each of the layers has been formed, trenches are formed in that layer. For example, when a first epitaxial layer has been formed, first trenches are formed in the epitaxial layer. Subsequently, when a second epitaxial layer has been formed, second trenches are formed in the epitaxial layer. Subsequently, when a third epitaxial layer has been formed, third trenches are formed in the third epitaxial layer.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: November 27, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Akio Ichimura, Satoshi Eguchi, Tetsuya Iida, Yuya Abiko
  • Patent number: 10120128
    Abstract: A semiconductor device includes: a first substrate; a surface insulating film formed over an upper surface of the first substrate; a BOX layer formed over the surface insulating film; an optical waveguide made of an SOI layer formed on the BOX layer; and a first interlayer insulating film formed over the BOX layer so as to cover the optical waveguide. The semiconductor device further includes: a trench formed in the surface insulating film and the first substrate below the optical waveguide; and a cladding layer made of a buried insulating film buried in the trench. A thickness of the BOX layer is 1 ?m or less, and a distance from an interface between the optical waveguide and the BOX layer to a bottom surface of the trench is 2 ?m or more.
    Type: Grant
    Filed: October 11, 2017
    Date of Patent: November 6, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Tetsuya Iida, Yasutaka Nakashiba
  • Publication number: 20180313056
    Abstract: A front loader including: a pair of masts provided to a machine body frame of a work vehicle in a detachable manner; a pair of lifting arms coupled to the masts in a vertically rotatable manner; and a work equipment mounted to the lifting arms. Each lifting arm includes a front lifting arm attached to one of the masts and a rear lifting arm attached to the work equipment, each of the front lifting arm and the rear lifting arm has a hollow, rectangular cross-section. The rear end portion of the front lifting arm is inserted into the front end portion of the rear lifting arm, and is welded. The side plate of the rear lifting arm at a location corresponding to the insertion portion has a protruding portion that extends along the side plate of the front lifting arm, and the protruding portion is welded.
    Type: Application
    Filed: October 27, 2015
    Publication date: November 1, 2018
    Applicant: Yanmar Co., Ltd.
    Inventor: Tetsuya IIDA
  • Publication number: 20180316122
    Abstract: A shield cover (1) made of metal is configured to be attached to a device and includes a cover body (10) configured to cover a shield target. Two planar attachment plates (11, 13) protrude from the cover body (10). Bolt insertion holes (11A, 13A) extend through the respective attachment plates (11, 13) in a thickness direction thereof and receive bolts (30) for attaching the shield cover (1) to the device. The attachment plates (11, 13) are configured to be attached to the device with brackets (20) sandwiched between the device and the attachment plates (11, 13). A rib (12) extends up along an edge of at least one of the attachment plates (11, 13) to reinforce a portion of the attachment plate (11, 13) that will not be sandwiched between the bolt (30) and the bracket (20).
    Type: Application
    Filed: October 12, 2016
    Publication date: November 1, 2018
    Inventors: Tetsuya Iida, Yosuke Kurono, Tatsuhiko Mizutani
  • Publication number: 20180309245
    Abstract: A shield connector (1) includes electric wires (11), a housing (20), a shield conductor (30), and a shield bracket (40). The shield bracket 40 includes a main bracket (50) including a conductor holding portion (51), first and second connection portions (61, 71) and an auxiliary bracket (80). The conductor holding portion (51) and the shield conductor (30) held thereby the cover outlet tubes (27) and the electric wires (11) from one side. The housing (20) includes first and second attachment protrusions (25, 26). The first connection portion (61) includes a first attachment piece (64) engaged with the first attachment protrusion (25). The auxiliary bracket (80) includes an auxiliary attachment piece (82) engaged with the second attachment protrusion (26). An overlapping plate (81) of the auxiliary bracket (80) is swaged onto the second connection portion (71) by a swaging piece (75) of the second connection portion (71).
    Type: Application
    Filed: October 14, 2016
    Publication date: October 25, 2018
    Inventors: Tetsuya IIDA, Yosuke KURONO, Tatsuhiko MIZUTANI
  • Publication number: 20180308795
    Abstract: A method of manufacturing a semiconductor device includes a step of: patterning a conductive film formed over an interlayer insulating film so as to form a coil and a conductive pattern in the same layer, and then forming unevennesses on a surface of the interlayer insulating film by etching a portion of the interlayer insulating film with using the coil and the conductive pattern as a mask.
    Type: Application
    Filed: April 16, 2018
    Publication date: October 25, 2018
    Applicant: Renesas Electronics Corporation
    Inventors: Shinichi UCHIDA, Yasutaka NAKASHIBA, Tetsuya IIDA, Shinichi KUWABARA
  • Publication number: 20180299706
    Abstract: To reduce a production cost of a semiconductor device and provide a semiconductor device having improved characteristics. A grating coupler has a plurality of projections separated from each other in an optical waveguide direction and a slab portion formed between any two of the projections adjacent to each other and formed integrally with them; a MOS optical modulator has a projection extending in the optical waveguide direction and slab portions formed on both sides of the projection, respectively, and formed integrally therewith. The projection of the grating coupler and the MOS optical modulator is formed of a first semiconductor layer, a second insulating layer, and a second semiconductor layer stacked successively on a first insulating layer, while the grating coupler and the MOS optical modulator each have a slab portion formed of the first semiconductor layer.
    Type: Application
    Filed: January 24, 2018
    Publication date: October 18, 2018
    Inventors: Shinichi KUWABARA, Yasutaka NAKASHIBA, Tetsuya IIDA, Shinichi WATANUKI
  • Publication number: 20180294593
    Abstract: A connector (10) includes terminals (20), wires (W) connected respectively to the terminals (20) and a housing (30) integrally holding the terminals (20) and the wires (W). The housing (30) includes a terminal holding portion 33 collectively holding the terminals (20) and wire holding portions (34) individually holding the wires (W). The wire holding portions (34) are flexible, project in the same direction from the terminal holding portion (33) and are separated from each other.
    Type: Application
    Filed: September 27, 2016
    Publication date: October 11, 2018
    Inventor: Tetsuya Iida
  • Publication number: 20180273531
    Abstract: The present invention relates to a pyrimidine compound or a pharmaceutically acceptable salt thereof represented by the following formula [I] wherein each symbol is as defined in the specification and a method of therapeutically or prophylactically treating an undesirable cell proliferation, comprising administering such a compound. The compound of the present invention has superior activity in suppressing undesirable cell proliferation, particularly, an antitumor activity, and is useful as an antitumor agent for the prophylaxis or treatment of cancer, rheumatism, and the like. In addition, the compound of the present invention can be a more effective antitumor agent when used in combination with other antitumor agents such as an alkylating agent or metabolism antagonist.
    Type: Application
    Filed: October 27, 2017
    Publication date: September 27, 2018
    Applicant: Japan Tobacco Inc.
    Inventors: Hisashi KAWASAKI, Hiroyuki ABE, Kazuhide HAYAKAWA, Tetsuya IIDA, Shinichi KIKUCHI, Takayuki YAMAGUCHI, Toyomichi NANAYAMA, Hironori KURACHI, Masahiro TAMARU, Yoshikazu HORI, Mitsuru TAKAHASHI, Takayuki YOSHIDA, Toshiyuki SAKAI
  • Publication number: 20180277518
    Abstract: An improvement is achieved in the reliability of a semiconductor device. A first semiconductor chip includes a semiconductor substrate, a wiring structure formed over the semiconductor substrate, an insulating film formed over the wiring structure, and a first insulating film formed over the insulating film. A second semiconductor chip includes a semiconductor substrate, a wiring structure formed over the semiconductor substrate, an insulating film formed over the wiring structure, and a second insulating film formed over the insulating film. The first insulating film forms an uppermost layer of the first semiconductor chip. The second insulating film forms an uppermost layer of the second semiconductor chip. Each of the first and second insulating films is made of a photosensitive resin film having an adhesive property.
    Type: Application
    Filed: January 3, 2018
    Publication date: September 27, 2018
    Inventors: Tetsuya IIDA, Yasutaka NAKASHIBA, Nobuya KOIKE
  • Publication number: 20180240905
    Abstract: To provide a semiconductor device including a power semiconductor element having improved reliability. The semiconductor device has a cell region and a peripheral region formed outside the cell region. The n type impurity concentration of n type column regions in the cell region is made higher than that of n type column regions comprised of an epitaxial layer in the peripheral region. Further, a charge balance is kept in each of the cell region and the peripheral region and each total electric charge is set so that a total electric charge of first p type column regions and a total electric charge of n type column regions in the cell region become larger than a total electric charge of third p type column regions and n type column regions comprised of an epitaxial layer in the peripheral region, respectively.
    Type: Application
    Filed: April 5, 2018
    Publication date: August 23, 2018
    Inventors: Satoshi EGUCHI, Tetsuya IIDA, Akio ICHIMURA, Yuya ABIKO