Patents by Inventor Tetsuya Iida

Tetsuya Iida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180158910
    Abstract: In a semiconductor device including a super junction structure that p-type columns and n-type columns are periodically arranged, a depth of a p-type column region in a cell region that a semiconductor element is formed is made shallower than a depth of a p-type column region in an intermediate region which surrounds the cell region. Thereby, a breakdown voltage of the cell region becomes lower than a breakdown voltage of the intermediate region. An avalanche breakdown phenomenon is caused to occur preferentially in the cell region in which even when an avalanche current is generated, the current is dispersed and smoothly flows. Thereby, it is possible to avoid local current constriction and breakage incidental thereto and consequently it becomes possible to improve avalanche resistance (an avalanche current amount with which a semiconductor device comes to be broken).
    Type: Application
    Filed: January 11, 2018
    Publication date: June 7, 2018
    Inventors: Yuya ABIKO, Satoshi EGUCHI, Akio ICHIMURA, Natsuo YAMAGUCHI, Tetsuya IIDA
  • Patent number: 9972713
    Abstract: To provide a semiconductor device including a power semiconductor element having improved reliability. The semiconductor device has a cell region and a peripheral region formed outside the cell region. The n type impurity concentration of n type column regions in the cell region is made higher than that of n type column regions comprised of an epitaxial layer in the peripheral region. Further, a charge balance is kept in each of the cell region and the peripheral region and each total electric charge is set so that a total electric charge of first p type column regions and a total electric charge of n type column regions in the cell region become larger than a total electric charge of third p type column regions and n type column regions comprised of an epitaxial layer in the peripheral region, respectively.
    Type: Grant
    Filed: May 6, 2015
    Date of Patent: May 15, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Satoshi Eguchi, Tetsuya Iida, Akio Ichimura, Yuya Abiko
  • Publication number: 20180128974
    Abstract: A semiconductor device includes: a first substrate; a surface insulating film formed over an upper surface of the first substrate; a BOX layer formed over the surface insulating film; an optical waveguide made of an SOI layer formed on the BOX layer; and a first interlayer insulating film formed over the BOX layer so as to cover the optical waveguide. The semiconductor device further includes: a trench formed in the surface insulating film and the first substrate below the optical waveguide; and a cladding layer made of a buried insulating film buried in the trench. A thickness of the BOX layer is 1 ?m or less, and a distance from an interface between the optical waveguide and the BOX layer to a bottom surface of the trench is 2 ?m or more.
    Type: Application
    Filed: October 11, 2017
    Publication date: May 10, 2018
    Inventors: Tetsuya IIDA, Yasutaka NAKASHIBA
  • Patent number: 9905644
    Abstract: In a semiconductor device including a super junction structure that p-type columns and n-type columns are periodically arranged, a depth of a p-type column region in a cell region that a semiconductor element is formed is made shallower than a depth of a p-type column region in an intermediate region which surrounds the cell region. Thereby, a breakdown voltage of the cell region becomes lower than a breakdown voltage of the intermediate region. An avalanche breakdown phenomenon is caused to occur preferentially in the cell region in which even when an avalanche current is generated, the current is dispersed and smoothly flows. Thereby, it is possible to avoid local current constriction and breakage incidental thereto and consequently it becomes possible to improve avalanche resistance (an avalanche current amount with which a semiconductor device comes to be broken).
    Type: Grant
    Filed: December 11, 2015
    Date of Patent: February 27, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Yuya Abiko, Satoshi Eguchi, Akio Ichimura, Natsuo Yamaguchi, Tetsuya Iida
  • Patent number: 9899446
    Abstract: A solid-state image sensing device capable of suppressing a dark current and transfer failure during a global shutter operation is provided. The solid-state image sensing device according to one embodiment includes: a semiconductor substrate having a main surface and a back surface being on the opposite side of the main surface; a well region arranged in contact with the main surface in the semiconductor substrate; a photoelectric conversion region arranged in contact with the main surface in the well region; a charge holding region arranged in contact with the main surface in the well region; a floating diffusion region arranged in contact with the main surface in the well region; a first transfer gate so formed as to face the well region and the charge holding region; and a second transfer gate so formed as to face the well region.
    Type: Grant
    Filed: December 8, 2016
    Date of Patent: February 20, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Tetsuya Iida, Yasutaka Nakashiba
  • Publication number: 20180019549
    Abstract: The electric shielded wire connection structure includes: a lower side case that accommodates a rotary electric machine; an upper side case that is positioned immediately above, and facing, the lower side case and accommodates an inverter; a plurality of electric wires that is arranged in a state where one end thereof is connected to a lower side terminal block immediately under the upper side case, the other end thereof is connected to an upper side terminal block at a wall surface side end part of the upper side case, and the plurality of electric wires is bent from the position immediately under the upper side case so as to face the wall surface; and a braided shielding member that shields the plurality of electric wires and is arranged for the plurality of electric wires only at the side opposite to the surface facing the upper side case.
    Type: Application
    Filed: October 16, 2015
    Publication date: January 18, 2018
    Applicants: TOYOTA JIDOSHA KABUSHIKI KAISHA, SUMITOMO WIRING SYSTEMS, LTD., AUTONETWORKS TECHNOLOGIES, LTD., SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Yasuhiro MAKIDO, Yousuke KURONO, Haruki KUSAMAKI, Tetsuya IIDA, Junpei NAKAMOTO, Takuya TATE, Hiroyuki MATSUOKA, Kouji FUKUMOTO, Daisuke HASHIMOTO, Toshiya HIROOKA
  • Publication number: 20180012959
    Abstract: A super junction structure having a high aspect ratio is formed. An epitaxial layer is dividedly formed in layers using the trench fill process, and when each of the layers has been formed, trenches are formed in that layer. For example, when a first epitaxial layer has been formed, first trenches are formed in the epitaxial layer. Subsequently, when a second epitaxial layer has been formed, second trenches are formed in the epitaxial layer. Subsequently, when a third epitaxial layer has been formed, third trenches are formed in the third epitaxial layer.
    Type: Application
    Filed: September 11, 2017
    Publication date: January 11, 2018
    Inventors: Akio ICHIMURA, Satoshi EGUCHI, Tetsuya IIDA, Yuya ABIKO
  • Publication number: 20180007298
    Abstract: To provide an imaging device capable of reducing the amount of data with a simple method. An imaging device includes: a plurality of sensor elements which is arranged in a matrix shape and each of which generates a photoelectric conversion voltage in accordance with an input light level; and a read circuit which is coupled to bit lines provided while being associated with respective columns of the sensor elements, and amplifies and reads the photoelectric conversion voltages generated in the sensor elements by being exposed at predetermined timing. The read circuit outputs differential data of the read photoelectric conversion voltages generated in the respective sensor elements that are adjacent to each other in the same row or column.
    Type: Application
    Filed: June 30, 2017
    Publication date: January 4, 2018
    Inventors: Tetsuya IIDA, Yasutaka NAKASHIBA
  • Patent number: 9786735
    Abstract: A super junction structure having a high aspect ratio is formed. An epitaxial layer is dividedly formed in layers using the trench fill process, and when each of the layers has been formed, trenches are formed in that layer. For example, when a first epitaxial layer has been formed, first trenches are formed in the epitaxial layer. Subsequently, when a second epitaxial layer has been formed, second trenches are formed in the epitaxial layer. Subsequently, when a third epitaxial layer has been formed, third trenches are formed in the third epitaxial layer.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: October 10, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Akio Ichimura, Satoshi Eguchi, Tetsuya Iida, Yuya Abiko
  • Patent number: 9761708
    Abstract: A semiconductor device includes a supporting substrate, an insulating film formed in a first region over the supporting substrate, a first semiconductor layer formed over the insulating film, a first epitaxial layer formed in an opening of the insulating film in a second region over the supporting substrate, an element isolation region formed between the first semiconductor layer and the first epitaxial layer, and a semiconductor element formed over each of the first semiconductor layer in the first region and the first epitaxial layer in the second region. The first semiconductor layer and the first epitaxial layer is spaced apart from each other by 5 ?m or more.
    Type: Grant
    Filed: May 4, 2016
    Date of Patent: September 12, 2017
    Assignee: Renesas Electronics Corporation
    Inventor: Tetsuya Iida
  • Patent number: 9742124
    Abstract: A terminal block including an electric wire, a shield material, a terminal, a housing and a shield bracket. The shield material is configured to cover at least a part of the electric wire. The electric wire is connected to the terminal. The housing is configured to accommodate the terminal. The shield bracket is fixed to the housing. The shield bracket is configured to hold the shield material, and includes a folding portion. The folding portion is configured to hold an end of the shield material by sandwiching the end of the shield material. The folding portion has a notch hole.
    Type: Grant
    Filed: February 10, 2015
    Date of Patent: August 22, 2017
    Assignees: TOYOTA JIDOSHA KABUSHIKI KAISHA, SUMITOMO WIRING SYSTEMS, LTD., AUTONETWORKS TECHNOLOGIES, LTD., SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Haruki Kusamaki, Hiroyuki Matsuoka, Takuya Tate, Yoshimi Uchida, Junpei Nakamoto, Tetsuya Iida, Daisuke Hashimoto, Kouji Fukumoto
  • Publication number: 20170229510
    Abstract: A solid-state image sensing device capable of suppressing a dark current and transfer failure during a global shutter operation is provided. The solid-state image sensing device according to one embodiment includes: a semiconductor substrate having a main surface and a back surface being on the opposite side of the main surface; a well region arranged in contact with the main surface in the semiconductor substrate; a photoelectric conversion region arranged in contact with the main surface in the well region; a charge holding region arranged in contact with the main surface in the well region; a floating diffusion region arranged in contact with the main surface in the well region; a first transfer gate so formed as to face the well region and the charge holding region; and a second transfer gate so formed as to face the well region.
    Type: Application
    Filed: December 8, 2016
    Publication date: August 10, 2017
    Inventors: Tetsuya IIDA, Yasutaka NAKASHIBA
  • Publication number: 20170114736
    Abstract: A control device for an internal combustion engine includes a throttle valve opening degree detector, an air bypass valve controller, and a torque reduction controller. The throttle valve opening degree detector detects an opening degree of a throttle valve which is provided downstream with respect to a compressor of a supercharger. The air bypass valve controller opens an air bypass valve based on a reduction change in the opening degree of the detected throttle valve. The air bypass valve is configured to open and close a bypass path. The torque reduction controller controls the throttle valve to reduce the opening degree of the throttle valve while an automatic transmission connected to the internal combustion engine is in an acceleration shifting in order to execute a torque reduction control. The air bypass valve controller maintains the air bypass valve in a close state during the torque reduction control.
    Type: Application
    Filed: October 21, 2016
    Publication date: April 27, 2017
    Applicant: HONDA MOTOR CO., LTD.
    Inventors: Tetsuya IIDA, Yuichi MASUKAKE, Masahiro TAKEUCHI
  • Publication number: 20170029418
    Abstract: The present invention relates to a pyrimidine compound or a pharmaceutically acceptable salt thereof represented by the following formula [I] wherein each symbol is as defined in the specification and a method of therapeutically or prophylactically treating an undesirable cell proliferation, comprising administering such a compound. The compound of the present invention has superior activity in suppressing undesirable cell proliferation, particularly, an antitumor activity, and is useful as an antitumor agent for the prophylaxis or treatment of cancer, rheumatism, and the like. In addition, the compound of the present invention can be a more effective antitumor agent when used in combination with other antitumor agents such as an alkylating agent or metabolism antagonist.
    Type: Application
    Filed: February 24, 2016
    Publication date: February 2, 2017
    Applicant: Japan Tobacco Inc.
    Inventors: Hisashi KAWASAKI, Hiroyuki ABE, Kazuhide HAYAKAWA, Tetsuya IIDA, Shinichi KIKUCHI, Takayuki YAMAGUCHI, Toyomichi NANAYAMA, Hironori KURACHI, Masahiro TAMARU, Yoshikazu HORI, Mitsuru TAKAHASHI, Takayuki YOSHIDA, Toshiyuki SAKAI
  • Publication number: 20160380390
    Abstract: A terminal block including an electric wire, a shield material, a terminal, a housing and a shield bracket. The shield material is configured to cover at least a part of the electric wire. The electric wire is connected to the terminal. The housing is configured to accommodate the terminal. The shield bracket is fixed to the housing. The shield bracket is configured to hold the shield material, and includes a folding portion. The folding portion is configured to hold an end of the shield material by sandwiching the end of the shield material. The folding portion has a notch hole.
    Type: Application
    Filed: February 10, 2015
    Publication date: December 29, 2016
    Applicants: TOYOTA JIDOSHA KABUSHIKI KAISHA, Sumitomo Wiring Systems, Ltd., Autonetworks Technologies, LTD., SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Haruki KUSAMAKI, Hiroyuki MATSUOKA, Takuya TATE, Yoshimi UCHIDA, Junpei NAKAMOTO, Tetsuya IIDA, Daisuke HASHIMOTO, Kouji FUKUMOTO
  • Publication number: 20160268369
    Abstract: A super junction structure having a high aspect ratio is formed. An epitaxial layer is dividedly formed in layers using the trench fill process, and when each of the layers has been formed, trenches are formed in that layer. For example, when a first epitaxial layer has been formed, first trenches are formed in the epitaxial layer. Subsequently, when a second epitaxial layer has been formed, second trenches are formed in the epitaxial layer. Subsequently, when a third epitaxial layer has been formed, third trenches are formed in the third epitaxial layer.
    Type: Application
    Filed: December 14, 2015
    Publication date: September 15, 2016
    Inventors: Akio ICHIMURA, Satoshi EGUCHI, Tetsuya IIDA, Yuya ABIKO
  • Publication number: 20160247915
    Abstract: A semiconductor device includes a supporting substrate, an insulating film formed in a first region over the supporting substrate, a first semiconductor layer formed over the insulating film, a first epitaxial layer formed in an opening of the insulating film in a second region over the supporting substrate, an element isolation region formed between the first semiconductor layer and the first epitaxial layer, and a semiconductor element formed over each of the first semiconductor layer in the first region and the first epitaxial layer in the second region. The first semiconductor layer and the first epitaxial layer is spaced apart from each other by 5 ?m or more.
    Type: Application
    Filed: May 4, 2016
    Publication date: August 25, 2016
    Inventor: Tetsuya IIDA
  • Publication number: 20160204192
    Abstract: In a semiconductor device including a super junction structure that p-type columns and n-type columns are periodically arranged, a depth of a p-type column region in a cell region that a semiconductor element is formed is made shallower than a depth of a p-type column region in an intermediate region which surrounds the cell region. Thereby, a breakdown voltage of the cell region becomes lower than a breakdown voltage of the intermediate region. An avalanche breakdown phenomenon is caused to occur preferentially in the cell region in which even when an avalanche current is generated, the current is dispersed and smoothly flows. Thereby, it is possible to avoid local current constriction and breakage incidental thereto and consequently it becomes possible to improve avalanche resistance (an avalanche current amount with which a semiconductor device comes to be broken).
    Type: Application
    Filed: December 11, 2015
    Publication date: July 14, 2016
    Inventors: Yuya ABIKO, Satoshi EGUCHI, Akio ICHIMURA, Natsuo YAMAGUCHI, Tetsuya IIDA
  • Patent number: D788184
    Type: Grant
    Filed: March 8, 2016
    Date of Patent: May 30, 2017
    Assignee: YANMAR CO., LTD.
    Inventors: Kiyoyuki Okuyama, Tetsuya Iida
  • Patent number: D788827
    Type: Grant
    Filed: March 8, 2016
    Date of Patent: June 6, 2017
    Assignee: YANMAR CO., LTD.
    Inventors: Kiyoyuki Okuyama, Tetsuya Iida