Patents by Inventor Tetsuya Iizuka

Tetsuya Iizuka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11784729
    Abstract: There is provided a calibration device including: a calibration signal supply unit configured to supply, as a calibration input signal, a multitone signal having tones at a plurality of frequency bands to a converter configured to multiply an input signal by each of a plurality of signal patterns and limit a band to obtain each of a plurality of bandpass signals, and reconstruct an output signal in accordance with the input signal from the plurality of bandpass signals; a calibration bandpass signal acquisition unit configured to acquire a plurality of calibration bandpass signals obtained by the converter in response to the multitone signal; and a calibration processing unit configured to calibrate a parameter for the reconstruction in the converter based on the plurality of calibration bandpass signals.
    Type: Grant
    Filed: June 5, 2022
    Date of Patent: October 10, 2023
    Assignees: ADVANTEST CORPORATION, The University of Tokyo
    Inventors: Koji Asami, Tetsuya Iizuka, Zolboo Byambadorj
  • Publication number: 20230105908
    Abstract: There is provided a calibration device including: a calibration signal supply unit configured to supply, as a calibration input signal, a multitone signal having tones at a plurality of frequency bands to a converter configured to multiply an input signal by each of a plurality of signal patterns and limit a band to obtain each of a plurality of bandpass signals, and reconstruct an output signal in accordance with the input signal from the plurality of bandpass signals; a calibration bandpass signal acquisition unit configured to acquire a plurality of calibration bandpass signals obtained by the converter in response to the multitone signal; and a calibration processing unit configured to calibrate a parameter for the reconstruction in the converter based on the plurality of calibration bandpass signals.
    Type: Application
    Filed: June 5, 2022
    Publication date: April 6, 2023
    Inventors: Koji ASAMI, Tetsuya IIZUKA, Zolboo BYAMBADORJ
  • Patent number: 11394376
    Abstract: An XTC circuit includes delay circuits, differentiated signal generating circuits, and an amplitude adjusting and adding circuit. A signal Da, which is one aggressor signal, is input to the differentiated signal generating circuit after being delayed by the delay circuit, and the differentiated signal generating circuit generates a differentiated signal having a differentiated waveform of the signal Da. In the amplitude adjusting and adding circuit, the differentiated signal generated by the differentiated signal generating circuit is amplitude-adjusted to become a current signal, and the differentiated signal after the amplitude adjustment is current-added to the signal Db.
    Type: Grant
    Filed: August 19, 2020
    Date of Patent: July 19, 2022
    Assignee: THINE ELECTRONICS, INC.
    Inventors: Yusuke Fujita, Satoshi Miura, Tetsuya Iizuka, Daigo Takahashi, Norihiko Nakasato
  • Patent number: 11290197
    Abstract: There is provided a calibration device including: a calibration signal supply unit configured to supply, as a calibration input signal, a multitone signal having tones in a plurality of frequency bands to a converter configured to multiply an input signal by each of a plurality of signal patterns and limit a band to obtain each of a plurality of bandpass signals, and reconstruct an output signal in accordance with an input signal from the plurality of bandpass signals; a calibration bandpass signal acquisition unit configured to acquire a plurality of calibration bandpass signals obtained by the converter in response to the multitone signal; and a calibration processing unit configured to calibrate a parameter for the reconstruction in the converter based on the plurality of calibration bandpass signals.
    Type: Grant
    Filed: March 24, 2021
    Date of Patent: March 29, 2022
    Assignees: ADVANTEST CORPORATION, TOUDAI TLO, Ltd.
    Inventors: Koji Asami, Tetsuya Iizuka, Zolboo Byambadorj
  • Patent number: 11220529
    Abstract: A method of producing a transgenic silkworm that spins bagworm silks and producing a large quantity of bagworm silks by transgenic technology is developed and provided. A gene encoding a modified bagworm Fib H and a transgenic silkworm in which the gene is introduced, wherein the gene is obtained by cloning a gene fragment encoding a bagworm Fib H-like polypeptide comprising a partial amino acid sequence of bagworm Fib H, and fusing the gene fragment to a gene fragment encoding silkworm-derived Fib H, are provided.
    Type: Grant
    Filed: October 16, 2017
    Date of Patent: January 11, 2022
    Assignee: NATIONAL AGRICULTURE AND FOOD RESEARCH ORGANIZATION
    Inventors: Naoyuki Yonemura, Tetsuya Iizuka, Kenichi Nakajima, Takuya Tsubota, Takao Suzuki, Hideki Sezutsu, Tsunenori Kameda, Taiyo Yoshioka
  • Publication number: 20210336710
    Abstract: There is provided a calibration device including: a calibration signal supply unit configured to supply, as a calibration input signal, a multitone signal having tones in a plurality of frequency bands to a converter configured to multiply an input signal by each of a plurality of signal patterns and limit a band to obtain each of a plurality of bandpass signals, and reconstruct an output signal in accordance with an input signal from the plurality of bandpass signals; a calibration bandpass signal acquisition unit configured to acquire a plurality of calibration bandpass signals obtained by the converter in response to the multitone signal; and a calibration processing unit configured to calibrate a parameter for the reconstruction in the converter based on the plurality of calibration bandpass signals.
    Type: Application
    Filed: March 24, 2021
    Publication date: October 28, 2021
    Inventors: Koji ASAMI, Tetsuya IIZUKA, Zolboo BYAMBADORJ
  • Publication number: 20210058078
    Abstract: An XTC circuit includes delay circuits, differentiated signal generating circuits, and an amplitude adjusting and adding circuit. A signal Da, which is one aggressor signal, is input to the differentiated signal generating circuit after being delayed by the delay circuit, and the differentiated signal generating circuit generates a differentiated signal having a differentiated waveform of the signal Da. In the amplitude adjusting and adding circuit, the differentiated signal generated by the differentiated signal generating circuit is amplitude-adjusted to become a current signal, and the differentiated signal after the amplitude adjustment is current-added to the signal Db.
    Type: Application
    Filed: August 19, 2020
    Publication date: February 25, 2021
    Applicant: THINE ELECTRONICS, INC.
    Inventors: Yusuke FUJITA, Satoshi MIURA, Tetsuya IIZUKA, Daigo TAKAHASHI, Norihiko NAKASATO
  • Publication number: 20200270288
    Abstract: An object is to provide a novel organophosphorus compound which can impart flame retardancy to an amorphous resin in a smaller addition amount without deteriorating heat resistance and transparency, and also can be applied to a wide range of resins, a flame retardant containing the same, and a method for producing an organophosphorus compound.
    Type: Application
    Filed: December 21, 2016
    Publication date: August 27, 2020
    Applicant: Maruzen Petrochemical Co., Ltd.
    Inventors: Tadashi YAMAZAKI, Tetsuya IIZUKA, Takashi TAKAHASHI, Yu KINAMI, Yusuke YKOO
  • Patent number: 10595390
    Abstract: The plasma torch has a nozzle and body. The nozzle has an inner nozzle and inner cap fastened to the body with the inner nozzle. Annular water passage and a plurality of independent water passages are formed between the inner nozzle and inner cap. Force applied when the inner cap is fastened to the nozzle base is transmitted via partitions. The torch body has a water supply port and drain port. At least one of the water supply port and drain port is configured as a groove extending on a plane crossing the axis and is connected to the water passage. When the nozzle is fastened to the torch body, one of the independent water passages communicates with the water supply port and another communicates with the water drain port. Rear end surface of inner nozzle is in contact with end surface of the nozzle base thereby obtaining electrical conductivity.
    Type: Grant
    Filed: August 18, 2014
    Date of Patent: March 17, 2020
    Assignee: KOIKE SANSO KOGYO CO., LTD.
    Inventors: Ryosuke Kimoto, Masatoshi Motoyama, Tetsuya Iizuka, Susumu Kanda, Katsuhiko Sakamoto, Akira Hurujo, Daiji Sakai
  • Patent number: 10429688
    Abstract: A liquid crystal display device includes a first substrate, a second substrate, a liquid crystal layer, first to fourth main light shields, a sub light shield, a spacer, and a spacer light shield disposed around the spacer. The spacer light shield includes a first part formed integrally with the second main light shield and the sub light shield between the first main light shield and the second main light shield, a second part formed integrally with the second main light shield, the third main light shield, and the sub light shield between the second main light shield and the third main light shield, and a third part formed integrally with the third main light shield and the sub light shield between the third main light shield and the fourth main light shield.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: October 1, 2019
    Assignee: Japan Display Inc.
    Inventors: Daichi Hosokawa, Tetsuya Iizuka
  • Publication number: 20190256565
    Abstract: A method of producing a transgenic silkworm that spins bagworm silks and producing a large quantity of bagworm silks by transgenic technology is developed and provided. A gene encoding a modified bagworm Fib H and a transgenic silkworm in which the gene is introduced, wherein the gene is obtained by cloning a gene fragment encoding a bagworm Fib H-like polypeptide comprising a partial amino acid sequence of bagworm Fib H, and fusing the gene fragment to a gene fragment encoding silkworm-derived Fib H, are provided.
    Type: Application
    Filed: October 16, 2017
    Publication date: August 22, 2019
    Applicant: National Agriculture and Food Research Organization
    Inventors: Naoyuki YONEMURA, Tetsuya IIZUKA, Kenichi NAKAJIMA, Takuya TSUBOTA, Takao SUZUKI, Hideki SEZUTSU, Tsunenori KAMEDA, Taiyo YOSHIOKA
  • Patent number: 10134906
    Abstract: According to one embodiment, a display device includes a first light shielding layer, a second light shielding layer, a first semiconductor layer, a second semiconductor layer, a gate line, a first source line, a second source line, a switching element, and a pixel electrode, wherein an area in which the first light shielding layer and the pixel electrode are opposed to each other and an area in which the second light shielding layer and the pixel electrode are opposed to each other are equal in size.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: November 20, 2018
    Assignee: JAPAN DISPLAY INC.
    Inventors: Naoki Miyanaga, Tetsuya Iizuka, Masanori Ando
  • Patent number: 10048543
    Abstract: In one embodiment, a liquid crystal display panel includes an array substrate and a counter substrate each having a display region and a peripheral region arranged adjacent to the display region. A resin layer is formed either one of the array substrate and the counter substrate. A protrusion in the shape of a wall is arranged on the resin layer with a gap between the protrusion and the substrate opposing the protrusion. A seal material is formed between the array substrate and the counter substrate, and arranged between a peripheral portion of the display region and the protrusion for attaching the array substrate and the counter substrate. A liquid crystal layer is formed in a surrounded region by the array substrate, the counter substrate and the seal material.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: August 14, 2018
    Assignee: JAPAN DISPLAY INC.
    Inventors: Katsuhiro Hoshina, Tetsuya Iizuka
  • Publication number: 20180069130
    Abstract: According to one embodiment, a display device includes a first light shielding layer, a second light shielding layer, a first semiconductor layer, a second semiconductor layer, a gate line, a first source line, a second source line, a switching element, and a pixel electrode, wherein an area in which the first light shielding layer and the pixel electrode are opposed to each other and an area in which the second light shielding layer and the pixel electrode are opposed to each other are equal in size.
    Type: Application
    Filed: November 9, 2017
    Publication date: March 8, 2018
    Applicant: JAPAN DISPLAY INC.
    Inventors: Naoki MIYANAGA, Tetsuya IIZUKA, Masanori ANDO
  • Patent number: 9887830
    Abstract: This embodiment relates to a clock data recovering apparatus capable of improving consecutive identical digits (CID) resistance. The clock data recovering apparatus includes a clock generating apparatus. The clock generating apparatus includes a signal selection unit, a phase detection unit, a phase control unit, a selection unit, a phase delay unit, a time measurement unit, and a phase selection unit. The phase delay unit includes a plurality of delay elements. The phase selection unit selectively outputs an output signal of any one of the plurality of delay elements as a feedback clock. The phase detection unit detects a phase relation between an edge signal and the feedback clock. The phase control unit outputs a control signal to control a signal selection operation by the phase selection unit such that a phase difference detected by the phase detection unit decreases, to the phase selection unit.
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: February 6, 2018
    Assignee: THINE ELECTRONICS, INC.
    Inventors: Kunihiro Asada, Tetsuya Iizuka, Norihito Tohge, Toru Nakura, Satoshi Miura, Yoshimichi Murakami
  • Patent number: 9847426
    Abstract: According to one embodiment, a display device includes a first light shielding layer, a second light shielding layer, a first semiconductor layer, a second semiconductor layer, a gate line, a first source line, a second source line, a switching element, and a pixel electrode, wherein an area in which the first light shielding layer and the pixel electrode are opposed to each other and an area in which the second light shielding layer and the pixel electrode are opposed to each other are equal in size.
    Type: Grant
    Filed: November 22, 2016
    Date of Patent: December 19, 2017
    Assignee: JAPAN DISPLAY INC.
    Inventors: Naoki Miyanaga, Tetsuya Iizuka, Masanori Ando
  • Patent number: 9810957
    Abstract: An array substrate includes a gate line extending in a first direction, a source line extending in a second direction orthogonally crossing the first direction and an auxiliary capacitance line having a trunk portion extending in the first direction so as to cross the source line and a branch portion branched from the trunk portion and extending along the source line. A switching element includes a drain line arranged under the auxiliary capacitance line so as to face the trunk portion and the branch portion thereof. A pixel electrode includes a main pixel electrode extending substantially in parallel to the source line and a contact portion electrically connected with the drain line. A counter substrate includes a couple of main common electrodes extending substantially in parallel to the main pixel electrode on the both sides sandwiching the main pixel electrode.
    Type: Grant
    Filed: July 13, 2015
    Date of Patent: November 7, 2017
    Assignee: Japan Display Inc.
    Inventors: Arihiro Takeda, Jin Hirosawa, Tetsuya Iizuka, Hirokazu Morimoto
  • Patent number: 9810959
    Abstract: A liquid crystal display including first and second substrates with a liquid crystal layer therebetween. The first substrate includes a semiconductor layer electrode electrically connected to a first source line on a first side of a position where the semiconductor layer intersects with a gate wire in a second direction, and to a contact portion on a second side of the position. A contact portion is arranged nearer the gate line than the main pixel electrode. The main pixel electrode extends from the contact portion in the second direction and is located nearer the second side than the first side. The contact portion is connected to the main pixel electrode only by a first portion of the main pixel electrode.
    Type: Grant
    Filed: August 10, 2015
    Date of Patent: November 7, 2017
    Assignee: Japan Display Inc.
    Inventors: Katsuhiro Hoshina, Tetsuya Iizuka, Masato Nakamura, Kazuya Daishi
  • Patent number: 9810936
    Abstract: According to one embodiment, a display panel includes an array substrate and a counter substrate. The array substrate includes an inorganic insulating film, a first wiring line, a second wiring line, an organic insulating film, a slit and a moisture-proof member. The slit is formed to extend through the organic insulating film between the first wiring line and the second wiring line. The moisture-proof member is filled in the slit and is in contact with the inorganic insulating film.
    Type: Grant
    Filed: September 5, 2013
    Date of Patent: November 7, 2017
    Assignee: Japan Display Inc.
    Inventors: Kazuya Daishi, Tetsuya Iizuka
  • Publication number: 20170214513
    Abstract: This embodiment relates to a clock data recovering apparatus capable of improving CID resistance. The clock data recovering apparatus includes a clock generating apparatus. The clock generating apparatus includes a signal selection unit, a phase detection unit, a phase control unit, a selection unit, a phase delay unit, a time measurement unit, and a phase selection unit. The phase delay unit includes a plurality of delay elements. The phase selection unit selectively outputs an output signal of any one of the plurality of delay elements as a feedback clock. The phase detection unit detects a phase relation between an edge signal and the feedback clock. The phase control unit outputs a control signal to control a signal selection operation by the phase selection unit such that a phase difference detected by the phase detection unit decreases, to the phase selection unit.
    Type: Application
    Filed: January 18, 2017
    Publication date: July 27, 2017
    Applicant: THINE ELECTRONICS, INC.
    Inventors: Kunihiro ASADA, Tetsuya IIZUKA, Norihito TOHGE, Toru NAKURA, Satoshi MIURA, Yoshimichi MURAKAMI