Patents by Inventor Tetsuya Iizuka

Tetsuya Iizuka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210058078
    Abstract: An XTC circuit includes delay circuits, differentiated signal generating circuits, and an amplitude adjusting and adding circuit. A signal Da, which is one aggressor signal, is input to the differentiated signal generating circuit after being delayed by the delay circuit, and the differentiated signal generating circuit generates a differentiated signal having a differentiated waveform of the signal Da. In the amplitude adjusting and adding circuit, the differentiated signal generated by the differentiated signal generating circuit is amplitude-adjusted to become a current signal, and the differentiated signal after the amplitude adjustment is current-added to the signal Db.
    Type: Application
    Filed: August 19, 2020
    Publication date: February 25, 2021
    Applicant: THINE ELECTRONICS, INC.
    Inventors: Yusuke FUJITA, Satoshi MIURA, Tetsuya IIZUKA, Daigo TAKAHASHI, Norihiko NAKASATO
  • Publication number: 20200270288
    Abstract: An object is to provide a novel organophosphorus compound which can impart flame retardancy to an amorphous resin in a smaller addition amount without deteriorating heat resistance and transparency, and also can be applied to a wide range of resins, a flame retardant containing the same, and a method for producing an organophosphorus compound.
    Type: Application
    Filed: December 21, 2016
    Publication date: August 27, 2020
    Applicant: Maruzen Petrochemical Co., Ltd.
    Inventors: Tadashi YAMAZAKI, Tetsuya IIZUKA, Takashi TAKAHASHI, Yu KINAMI, Yusuke YKOO
  • Patent number: 10595390
    Abstract: The plasma torch has a nozzle and body. The nozzle has an inner nozzle and inner cap fastened to the body with the inner nozzle. Annular water passage and a plurality of independent water passages are formed between the inner nozzle and inner cap. Force applied when the inner cap is fastened to the nozzle base is transmitted via partitions. The torch body has a water supply port and drain port. At least one of the water supply port and drain port is configured as a groove extending on a plane crossing the axis and is connected to the water passage. When the nozzle is fastened to the torch body, one of the independent water passages communicates with the water supply port and another communicates with the water drain port. Rear end surface of inner nozzle is in contact with end surface of the nozzle base thereby obtaining electrical conductivity.
    Type: Grant
    Filed: August 18, 2014
    Date of Patent: March 17, 2020
    Assignee: KOIKE SANSO KOGYO CO., LTD.
    Inventors: Ryosuke Kimoto, Masatoshi Motoyama, Tetsuya Iizuka, Susumu Kanda, Katsuhiko Sakamoto, Akira Hurujo, Daiji Sakai
  • Patent number: 10429688
    Abstract: A liquid crystal display device includes a first substrate, a second substrate, a liquid crystal layer, first to fourth main light shields, a sub light shield, a spacer, and a spacer light shield disposed around the spacer. The spacer light shield includes a first part formed integrally with the second main light shield and the sub light shield between the first main light shield and the second main light shield, a second part formed integrally with the second main light shield, the third main light shield, and the sub light shield between the second main light shield and the third main light shield, and a third part formed integrally with the third main light shield and the sub light shield between the third main light shield and the fourth main light shield.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: October 1, 2019
    Assignee: Japan Display Inc.
    Inventors: Daichi Hosokawa, Tetsuya Iizuka
  • Publication number: 20190256565
    Abstract: A method of producing a transgenic silkworm that spins bagworm silks and producing a large quantity of bagworm silks by transgenic technology is developed and provided. A gene encoding a modified bagworm Fib H and a transgenic silkworm in which the gene is introduced, wherein the gene is obtained by cloning a gene fragment encoding a bagworm Fib H-like polypeptide comprising a partial amino acid sequence of bagworm Fib H, and fusing the gene fragment to a gene fragment encoding silkworm-derived Fib H, are provided.
    Type: Application
    Filed: October 16, 2017
    Publication date: August 22, 2019
    Applicant: National Agriculture and Food Research Organization
    Inventors: Naoyuki YONEMURA, Tetsuya IIZUKA, Kenichi NAKAJIMA, Takuya TSUBOTA, Takao SUZUKI, Hideki SEZUTSU, Tsunenori KAMEDA, Taiyo YOSHIOKA
  • Patent number: 10134906
    Abstract: According to one embodiment, a display device includes a first light shielding layer, a second light shielding layer, a first semiconductor layer, a second semiconductor layer, a gate line, a first source line, a second source line, a switching element, and a pixel electrode, wherein an area in which the first light shielding layer and the pixel electrode are opposed to each other and an area in which the second light shielding layer and the pixel electrode are opposed to each other are equal in size.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: November 20, 2018
    Assignee: JAPAN DISPLAY INC.
    Inventors: Naoki Miyanaga, Tetsuya Iizuka, Masanori Ando
  • Patent number: 10048543
    Abstract: In one embodiment, a liquid crystal display panel includes an array substrate and a counter substrate each having a display region and a peripheral region arranged adjacent to the display region. A resin layer is formed either one of the array substrate and the counter substrate. A protrusion in the shape of a wall is arranged on the resin layer with a gap between the protrusion and the substrate opposing the protrusion. A seal material is formed between the array substrate and the counter substrate, and arranged between a peripheral portion of the display region and the protrusion for attaching the array substrate and the counter substrate. A liquid crystal layer is formed in a surrounded region by the array substrate, the counter substrate and the seal material.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: August 14, 2018
    Assignee: JAPAN DISPLAY INC.
    Inventors: Katsuhiro Hoshina, Tetsuya Iizuka
  • Publication number: 20180069130
    Abstract: According to one embodiment, a display device includes a first light shielding layer, a second light shielding layer, a first semiconductor layer, a second semiconductor layer, a gate line, a first source line, a second source line, a switching element, and a pixel electrode, wherein an area in which the first light shielding layer and the pixel electrode are opposed to each other and an area in which the second light shielding layer and the pixel electrode are opposed to each other are equal in size.
    Type: Application
    Filed: November 9, 2017
    Publication date: March 8, 2018
    Applicant: JAPAN DISPLAY INC.
    Inventors: Naoki MIYANAGA, Tetsuya IIZUKA, Masanori ANDO
  • Patent number: 9887830
    Abstract: This embodiment relates to a clock data recovering apparatus capable of improving consecutive identical digits (CID) resistance. The clock data recovering apparatus includes a clock generating apparatus. The clock generating apparatus includes a signal selection unit, a phase detection unit, a phase control unit, a selection unit, a phase delay unit, a time measurement unit, and a phase selection unit. The phase delay unit includes a plurality of delay elements. The phase selection unit selectively outputs an output signal of any one of the plurality of delay elements as a feedback clock. The phase detection unit detects a phase relation between an edge signal and the feedback clock. The phase control unit outputs a control signal to control a signal selection operation by the phase selection unit such that a phase difference detected by the phase detection unit decreases, to the phase selection unit.
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: February 6, 2018
    Assignee: THINE ELECTRONICS, INC.
    Inventors: Kunihiro Asada, Tetsuya Iizuka, Norihito Tohge, Toru Nakura, Satoshi Miura, Yoshimichi Murakami
  • Patent number: 9847426
    Abstract: According to one embodiment, a display device includes a first light shielding layer, a second light shielding layer, a first semiconductor layer, a second semiconductor layer, a gate line, a first source line, a second source line, a switching element, and a pixel electrode, wherein an area in which the first light shielding layer and the pixel electrode are opposed to each other and an area in which the second light shielding layer and the pixel electrode are opposed to each other are equal in size.
    Type: Grant
    Filed: November 22, 2016
    Date of Patent: December 19, 2017
    Assignee: JAPAN DISPLAY INC.
    Inventors: Naoki Miyanaga, Tetsuya Iizuka, Masanori Ando
  • Patent number: 9810957
    Abstract: An array substrate includes a gate line extending in a first direction, a source line extending in a second direction orthogonally crossing the first direction and an auxiliary capacitance line having a trunk portion extending in the first direction so as to cross the source line and a branch portion branched from the trunk portion and extending along the source line. A switching element includes a drain line arranged under the auxiliary capacitance line so as to face the trunk portion and the branch portion thereof. A pixel electrode includes a main pixel electrode extending substantially in parallel to the source line and a contact portion electrically connected with the drain line. A counter substrate includes a couple of main common electrodes extending substantially in parallel to the main pixel electrode on the both sides sandwiching the main pixel electrode.
    Type: Grant
    Filed: July 13, 2015
    Date of Patent: November 7, 2017
    Assignee: Japan Display Inc.
    Inventors: Arihiro Takeda, Jin Hirosawa, Tetsuya Iizuka, Hirokazu Morimoto
  • Patent number: 9810959
    Abstract: A liquid crystal display including first and second substrates with a liquid crystal layer therebetween. The first substrate includes a semiconductor layer electrode electrically connected to a first source line on a first side of a position where the semiconductor layer intersects with a gate wire in a second direction, and to a contact portion on a second side of the position. A contact portion is arranged nearer the gate line than the main pixel electrode. The main pixel electrode extends from the contact portion in the second direction and is located nearer the second side than the first side. The contact portion is connected to the main pixel electrode only by a first portion of the main pixel electrode.
    Type: Grant
    Filed: August 10, 2015
    Date of Patent: November 7, 2017
    Assignee: Japan Display Inc.
    Inventors: Katsuhiro Hoshina, Tetsuya Iizuka, Masato Nakamura, Kazuya Daishi
  • Patent number: 9810936
    Abstract: According to one embodiment, a display panel includes an array substrate and a counter substrate. The array substrate includes an inorganic insulating film, a first wiring line, a second wiring line, an organic insulating film, a slit and a moisture-proof member. The slit is formed to extend through the organic insulating film between the first wiring line and the second wiring line. The moisture-proof member is filled in the slit and is in contact with the inorganic insulating film.
    Type: Grant
    Filed: September 5, 2013
    Date of Patent: November 7, 2017
    Assignee: Japan Display Inc.
    Inventors: Kazuya Daishi, Tetsuya Iizuka
  • Publication number: 20170214513
    Abstract: This embodiment relates to a clock data recovering apparatus capable of improving CID resistance. The clock data recovering apparatus includes a clock generating apparatus. The clock generating apparatus includes a signal selection unit, a phase detection unit, a phase control unit, a selection unit, a phase delay unit, a time measurement unit, and a phase selection unit. The phase delay unit includes a plurality of delay elements. The phase selection unit selectively outputs an output signal of any one of the plurality of delay elements as a feedback clock. The phase detection unit detects a phase relation between an edge signal and the feedback clock. The phase control unit outputs a control signal to control a signal selection operation by the phase selection unit such that a phase difference detected by the phase detection unit decreases, to the phase selection unit.
    Type: Application
    Filed: January 18, 2017
    Publication date: July 27, 2017
    Applicant: THINE ELECTRONICS, INC.
    Inventors: Kunihiro ASADA, Tetsuya IIZUKA, Norihito TOHGE, Toru NAKURA, Satoshi MIURA, Yoshimichi MURAKAMI
  • Patent number: 9658505
    Abstract: A display device includes an insulating substrate, a semiconductor layer formed of polycrystalline silicon, including a first impurity area, a second impurity area, and a channel area, an insulating film which covers the semiconductor layer, a gate electrode formed on the insulating film and opposed to the channel area, a source line electrically connected to the first impurity area, an electrode electrically connected to the second impurity area, and a light-shielding film located between the insulating substrate and the semiconductor layer, disposed at a position displaced from a position opposed to the source line, and opposed to an area including a boundary between the channel area and the second impurity area.
    Type: Grant
    Filed: April 16, 2015
    Date of Patent: May 23, 2017
    Assignee: Japan Display Inc.
    Inventors: Tatsuya Ishii, Tetsuya Iizuka
  • Patent number: 9548322
    Abstract: According to one embodiment, a wiring substrate includes a pad group of a first pad to supply a power source voltage of low level, a second pad to supply a power source voltage of high level, and a third pad to supply a necessary signal for displaying an image, a common line, a first connection line to connect the first pad with the common line, a second connection line to connect the second pad with the common line, and a third connection line to connect the third pad with the common line, wherein the first connection line and the second connection line are formed of polysilicon in which no impurity is doped, and the third connection line and the common line are formed of polysilicon in which an impurity is doped.
    Type: Grant
    Filed: December 4, 2014
    Date of Patent: January 17, 2017
    Assignee: Japan Display Inc.
    Inventors: Takamitsu Fujimoto, Tetsuya Iizuka
  • Patent number: 9543326
    Abstract: According to one embodiment, a display device includes a first light shielding layer, a second light shielding layer, a first semiconductor layer, a second semiconductor layer, a gate line, a first source line, a second source line, a switching element, and a pixel electrode, wherein an area in which the first light shielding layer and the pixel electrode are opposed to each other and an area in which the second light shielding layer and the pixel electrode are opposed to each other are equal in size.
    Type: Grant
    Filed: August 4, 2015
    Date of Patent: January 10, 2017
    Assignee: Japan Display Inc.
    Inventors: Naoki Miyanaga, Tetsuya Iizuka, Masanori Ando
  • Patent number: 9470936
    Abstract: In one embodiment, a first shield electrode and a second shield electrode are arranged on a first substrate. A first source line and a second source line are arranged facing the first and second shield electrodes through an insulating layer, respectively. A first main common electrode and a second main common electrode are formed facing the first and second source lines through an insulating layer, respectively. A main pixel electrode is formed so as to locate between the first and second main common electrodes. A second substrate includes a third main common electrode and a fourth main common electrode facing the first and second main common electrodes, respectively. A liquid crystal layer is held between the first and second substrates. The first, second, third and fourth main common electrodes are set to the same electric potential.
    Type: Grant
    Filed: June 17, 2015
    Date of Patent: October 18, 2016
    Assignee: Japan Display, Inc.
    Inventors: Koji Yamamoto, Tetsuya Iizuka
  • Publication number: 20160286637
    Abstract: [A problem to be solved] To provide a plasma torch in which a nozzle can be effectively cooled to an ejecting hole of plasm arc and which has a stable electrification properties [Measures to solve the problem] The plasma torch of the present invention has nozzle A and the torch body B. The nozzle A has the inner nozzle 2 and the inner cap 3 which is fastened to the torch body with the inner nozzle 2. The annular water passage 8 and a plurality of independent water passages 9 are formed between the inner nozzle 2 and the inner cap 3. A fastening force applied when the inner cap 3 is fastened to the nozzle base 14 is transmitted via the partitions 2f. The torch body B has the water supply port 20 and the water drain port 21. At least one of the water supply port 20 and the water drain port 21 is configured as a groove which extends on a plane which crosses the axis and which is connected to the water passage.
    Type: Application
    Filed: August 18, 2014
    Publication date: September 29, 2016
    Applicant: Koike Sanso Kogyo Co., Ltd.
    Inventors: Ryosuke KIMOTO, Masatoshi MOTOYAMA, Tetsuya IIZUKA, Susumu KANDA, Katsuhiko SAKAMOTO, Akira HURUJO, Daiji SAKAI
  • Publication number: 20160141319
    Abstract: A solid-state imaging device having an arrangement in which well contact is achieved for each pixel is provided. In the solid-state imaging device, a well contact part is formed in an activation region of a photoelectric conversion portion. The well contact part fixes a well in which the photoelectric conversion portion and transistors of the pixel are provided at a predetermined potential.
    Type: Application
    Filed: January 22, 2016
    Publication date: May 19, 2016
    Inventors: Takashi ABE, Ryoji SUZUKI, Keiji MABUCHI, Tetsuya IIZUKA, Takahisa UENO, Tsutomu HARUTA