Abstract: In a semiconductor device such as a CCD solid-state imager having terminals connected with protection transistors, a strength against a static electricity applied between a terminal and a ground (GND) and a strength against a static electricity applied between a terminal and a substrate and a strength against a static electricity between terminals can be improved.

Abstract: An image sensing system includes a solid-state image sensor having at least two horizontal shift registers for providing monochromatic multichannel signals, and a signal processing circuit for combining the signals into a monochromatic composite signal. The signal processing circuit includes a first combining circuit for producing a first output signal by selecting one of the multichannel signals alternately at regular intervals, a second combining circuit for adding together the multichannel signals to produce a second, and a third combining circuit for producing a composite signal by output signal combining the first and second signals through selection or addition. Thus, this system can produce the composite signal in either of two different combining modes, one of which is superior in frequency characteristic and the other of which can provide high S/N signals.

Abstract: An amplifier circuit includes two inverter circuits. Each inverter circuit provides an output signal in response to a respective input signal. The inverter circuits are supplied with a power source voltage through a MOS transistor circuit. The MOS transistor circuit includes two MOS transistors each having gate electrodes supplied with the output of the inverter circuits.

Abstract: A CCD shift register which is improved in the transfer efficiency with a minimal decrease in the amount of electric charge that can be handled. The CCD shift register has an array of transfer electrodes, each comprising a pair of storage and transfer gate electrodes, which are formed on a semiconductor substrate through a gate insulator. A semiconductor region under each storage gate electrode is divided into a plurality of subregions by using impurities.

Abstract: A CCD imager designed to combine two consecutive lines of signal charges into a signal line to provide a picture signal according to a television system, such as NTSC with an image sensor having a photosensor array, or another television system, such as HDTV or EDTV. When the NTSC mode is selected by a selector, the vertical shift registers are clocked rapidly so that a vertical scan is repeated twice in each horizontal scanning period to reduce the number of scanning lines in half.

Abstract: A liquid crystal display device includes first and second substrate and a liquid crystal layer sealed between the substrates. A plurality of pixel elements are formed in a matrix pattern on the first substrate, and a plurality of driving nonlinear resistance elements are formed on the first substrate and electrically connected to the pixel electrodes, respectively. A plurality of parallel wiring electrodes are formed on the first substrate, respectively extending in parallel to the columns of the pixel electrodes, and electrically connected to the respective nonlinear resistance elements on the respective columns of the pixel electrodes. Each wiring electrode is divided at a dividing portion and has a pair of divided ends. Protecting nonlinear resistance elements are respectively formed on the divided ends of each wiring electrode so as to reduce potential difference between the divided ends when static electricity is generated at the dividing portions.

Abstract: An interline transfer or frame interline transfer CCD solid image sensor is adapted to read out signal charges from light receiving sections of a matrix array by means of vertical charge transfer sections and horizontal charge transfer sections. A plurality of horizontal charge transfer sections are formed for lowering the horizontal transfer frequency. The voltage transition in the transfer gate across the horizontal charge transfer sections is caused to occur stepwise or temporally slowly to improve the transfer efficiency across the horizontal charge transfer sections. A smear drain region for sweeping out unnecessary charges is formed along the horizontal charge transfer sections. The transfer electrode of the horizontal charge transfer sections connected to the busline wiring is patterned to clear contact holes provided in the smear drain region to provide for positive overflow without increasing the chip area.

Abstract: A structure of a solid-state image sensing device applicable to an HDVS is disclosed in which at least one of the transmission paths for the drive pulses used for driving vertical registers and horizontal registers can achieve reduced propagation delays and signal distortions of the drive pulses. In the first preferred embodiment, a control gate for controlling the transfer of signal charges between the horizontal registers is constituted by a first polycrystalline silicon layer, a metal wiring layer is formed and is connected to the first polycrystalline silicon layer via contact regions and transfer electrodes provided for driving the horizontal registers are constituted by second and third semiconductor layers placed between the first polycrystalline silicon layer and the metal wiring layer without contacting the contact regions.

Abstract: With the CCD imager of the present invention, signal charges from the image area are transferred by plural juxtaposed read-out registers. The storage region of the read-out registers, through which electrical charges are transmitted, is narrower in width at the image area side and broader in width at the other read-out register side. By virtue of such arrangement of the storage area, there is formed a potential which becomes shallow at the side of the image area and becomes deep at the side of the other read-out registers. By such potential, signal charge transfer efficiency between the read-out registers is improved.

Abstract: A semiconductor memory device includes first and second n.sup.+ -type regions formed in the surface area of a p-type substrate; a floating gate insulatively formed over a channel region between the first and second n.sup.+ -type regions; and a control gate disposed to face the floating gate. The area of the portion of the control gate which faces the floating gate is set to be smaller than the effective area of the portion of the floating gate which faces an active region including the first and second n.sup.+ -type regions and channel region.

Abstract: An output circuit for CCD imager devices or CCD delay devices is disclosed in which a depletion type second MIS transistor is connected to the drain side of a first MIS transistor constituting a source follower adapted for converting transferred signal signals into an electrical voltage, and an output voltage is supplied to the gate of the second MIS transistor. This depletion type second MIS transistor causes the drain potential of the first MIS transistor to be changed in phase with the input electrical charges to reduce the gate-to-drain capacitance of the first MIS transistor to improve the charge-to-voltage conversion gain.

Abstract: An automatic gain control circuit having a variable gain amplifier circuit, a signal level detecting circuit connected to the variable gain amplifier circuit for generating a detect signal the level of which changes in response to a signal level of an output signal of the variable gain amplifier circuit, and a gain control circuit for controlling the gain of the variable gain amplifier circuit in accordance with the signal level of the detect signal, and the gain control circuit having a differential amplifier circuit having first and second input terminals, the first and second input terminals being connected to the signal level detecting circuit for receiving the detect signal, a first reference voltage source connected to the first input terminal of the differential amplifier so that a first predetermined voltage is provided instead of the signal level of the detect signal in response to the signal level of the detect signal and a second reference voltage source connected to the second input terminal of th

Abstract: Semiconductor integrated circuit of the present invention comprises a signal output terminal, a load circuit connected to the signal output terminal, a transistor circuit which is constituted by at least one first channel MOS transistor and has an output terminal connected to the signal output terminal and an input terminal connected to a signal input terminal, and a first channel enhancement type MOS transistor that is inserted between the transistor circuit's output terminal and the signal output terminal and is made normally in an on state. It is an object of the present invention to provide a highly reliable semiconductor integrated circuit in which no deterioration of characteristics due to hot carriers occurs even when the circuit is constituted using short channel MOS transistors with an effective channel length of about 1 micron or less.

Abstract: The threshold voltage of bit line percharge/equalize MOS transistors is smaller than that of normally ON type bit line pull-up transistors. With this feature, there is no current flows through a bit line from power source V.sub.DD during a read-out operation. The voltage difference between a pair of bit lines can be increased at high speed, thereby increasing the read-out speed.

Abstract: The present invention relates to a plasma processing apparatus capable of obtaining a satisfactory plasma arc and a processing method used by this plasma processing apparatus.The plasma processing apparatus is constructed to vary an electric current or a voltage during start up at a fixed period for a fixed time. The plasma processing apparatus has a plasma power source capable of controlling an electric current or a voltage applied to a plasma torch, and an electrode and a nozzle are communicated by means of an electrification in the plasma torch.In a method for performing a plasma process by a plasma processing apparatus, a mixing gas has a ratio of Hydrogen to Argon in a range from 5 to 20 Vol %, and a frequency of a plasma electric current is controlled in a range from 10 to 30 KHz.

Abstract: A static memory has an address transition detector, an input data transition detector and a pulse signal generator. When a detector detects that an input address or input data has changed, the pulse signal generator produces a pulse signal having a width longer than the shorter of the data-reading or data-writing cycle. This pulse signal controls the period of time during which a penetrating DC current flows between two power sources via some of the components of the memory.

Abstract: Semiconductor integrated circuit of the present invention comprises a signal output terminal, a load circuit connected to the signal output terminal, a transistor circuit which is constituted by at least one first channel MOS transistor and has an output terminal connected to the signal output terminal and an input terminal connected to a signal input terminal, and a first channel enhancement type MOS transistor that is inserted between the transistor circuit's output terminal and the signal output terminal and is made normally in an on state. It is an object of the present invention to provide a highly reliable semiconductor integrated circuit in which no deterioration of characteristics due to hot carriers occurs even when the circuit is constituted using short channel MOS transistors with an effective channel length of about 1 micron or less.

Abstract: An MOS semiconductor device comprises a MOS operation circuit including a plurality of MOS transistors each with a reduced channel length and an operation voltage setting circuit for supplying an operation voltage lower than the power source voltage between the first and second operation voltage receiving terminals. The back gates of the MOS transistors in the MOS operation circuit are connected to a power source terminal or ground. The operation voltage setting circuit is inserted between the MOS operation circuit and either the power source terminal or ground and develops a voltage drop in accordance with the operating current flowing through the MOS operation circuit.

Abstract: In a semiconductor device according to the invention, first and second voltage dropping circuits, for generating voltages respectively having smaller values than that of an external power supply voltage, are provided. The first voltage dropping circuit, which consumes relatively less power, is always in the operative mode, and the second voltage dropping circuit, which consumes more power than that of the first voltage dropping circuit, is operated during an interval other than a standby interval. The voltages generated by the first and second voltage dropping circuits are supplied to an internal power supply line in parallel with each other.

Abstract: A self-refresh control circuit for a dynamic memory device having memory cells and a self-refresh circuit on a single chip. The circuit includes a leak current monitor circuit representing the leakage of a memory cell and an inverter circuit for detecting the leakage of the monitor circuit so as to control the refresh operation automatically.