Abstract: In a dynamic RAM, the refreshing operation is performed during one cycle of the read or write operation. A switch circuit selects either a row address signal output from address input circuit or a refresh row address signal output from a refresh circuit. By controlling the switch circuit by a switch selector, the refresh is performed during the operation delay time of the address input circuit or an input/output circuit for inputting and outputting data.

Abstract: The present invention relates to a gas cutting torch characterized in that a buffer is included within the preheating oxygen-supplying passage which is arranged in the inside of the injector head capable of supplying the preheated oxygen.

Abstract: Disclosed is a semiconductor device in which IC chips, tested and evaluated as good, are mounted on a silicon substrate, and interconnection wiring layers and pads for IC chips are provided on the substrate with an insulation film interposed therebetween.

Abstract: A semiconductor memory device having a floating gate transistor and an insulated gate transistor, is provided a p-type semiconductor substrate, first, second and third semiconductor regions which are formed in the surface area of the substrate, a floating gate electrode capacitively coupled through a first insulating layer to a current path including the first and second semiconductor regions, a control gate electrode capacitively coupled through a second insulating layer to the floating gate electrode, and an insulated gate electrode which is formed through a first insulating layer on that portion of the substrate which lies between the second and third semiconductor regions. The first insulating layer of the semiconductor memory device is formed on that portion of the substrate which lies between the first and second semiconductor regions. The control gate electrode is a fourth semiconductor region which is formed in the surface area of the substrate.

Abstract: The dynamic memory device of the present invention is formed on an integrated semiconductor substrate subjected to alpha radiation and comprises a switching transistor having a switching terminal, an input-output terminal and a memory terminal; a bit line couple to said input-output terminal for supplying a charge to said transistor; a word line coupled to said switching terminal for controlling the switching of said transistor; and, an R-C circuit coupled to the memory terminal and comprising a charge storage capacitor for storing the charge supplied from said bit line and for substantially preventing loss of the stored charge due to particle radiation.

Abstract: A source region and a drain region are formed in a semiconductor layer, a thin insulating layer of SiO.sub.2 is formed on the semiconductor layer, and a gate electrode is formed thereover. Al metal forms ohmic contacts with the source and drain regions to provide a source electrode and a drain electrode, respectively. Al diffused in the drain region remains within the drain region, and the drain region and the substrate region form a p-n junction. Al diffused in the source region traverses the source region and reaches the substrate region to form an ohmic contact between the source region and the substrate region.

Abstract: A source region and a drain region are formed in a semiconductor layer, a thin insulating layer of SiO.sub.2 is formed on the semiconductor layer, and a gate electrode is formed thereover. Al metal forms ohmic contacts with the source and drain regions to provide a source electrode and a drain electrode, respectively. Al diffused in the drain region remains within the drain region, and the drain region and the substrate region form a p-n junction. Al diffused in the source region traverses the source region and reaches the substrate region to form an ohmic contact between the source region and the substrate region.

Abstract: A semiconductor memory device has a plurality of memory cells arranged in a two-dimensional matrix array, word lines for connecting memory cells of each row to a row decoder, and bit lines for connecting memory cells of each column to a column decoder. The word lines include first word lines each of which is connected to several memory cells in each column section of one row. The word lines also include a second word line connected to the first word lines of each row through corresponding switches. In response to a column address signal, one of the switches of each row is turned on, so that one of the first word lines is connected to the corresponding second word line.

Abstract: A signal input circuit particularly well suited for use in MOS integrated circuits. The signal input circuit includes: and input gate circuit for receiving an input signal and an enable control signal, and for generating an output signal equal to the input signal when the enable control signal is in an "enable" state, and for providing a high output impedance when the enable control signal is in a "disable" state; and a holding circuit coupled to an output of the input gate circuit and to receiving the enable control signal, for holding, during the disable state, the output state of the input gate circuit immediately before the enable control signal changes to a disable state, the output impedance being high when the enable control signal is in an enable state.

Abstract: In the semiconductor memory device according to the present invention, when there is a defective portion in the memory cells, those memory cells are replaced by redundant memory cells. When defective portions are discovered in the memory cells, the fuse elements corresponding to the memory cells having the defective portions are cut off. Voltages of the select lines connected to the memory cells having the defective portions are held at an L level by the resistors. Due to this, the memory cells having the defective portions are not selected.

Abstract: A charge pump bias generator constructed of P channel MOSFETs in an N type substrate is used to provide a negative bias to a P well containing active N-channel MOSFET circuit elements to reverse bias the N type source to P well junctions. Since the charge pump uses P channel FETs in an N substrate with the N substrate connected to the positive power supply, parasitic minority carrier injection by the charge pump is prevented.

Abstract: A semiconductor memory device comprises a flip-flop circuit composed of two inverters each including two series-connected resistors as load elements, the input and output terminals of one of the inverters are respectively connected to the output and input terminals of the other inverter, and two capacitors whose first terminals are connected to the junctions of the two resistors and whose second terminals are connected to the output terminals of the two inverters.

Abstract: A semiconductor memory device which comprises a memory section formed of a first substrate region of a first conductivity type and a first MOS transistor of a second conductivity type which is formed in the first substrate region to act as a transfer gate; and a peripheral circuit constituted by a second MOS transistor of a first conductivity type and a third MOS transistor of a second conductivity type. A second substrate region of a second conductivity type in which the second MOS transistor is formed substantially surrounds the memory section.

Abstract: A semiconductor memory circuit includes a power supply terminal; a first MOS transistor; a second MOS transistor whose source, gate and drain are respectively connected to the source, drain and gate of the first MOS transistor; first and second resistors connected between the power supply terminal and the drains of the first and second MOS transistors; a data line; a word line; and a third MOS transistor whose current path is connected between the drain of the first MOS transistor and data line, and whose gate is connected to the word line. The semiconductor memory circuit further includes a write control line whose potential is set at a high level when a readout operation is effected. The sources of the first and second MOS transistors are jointly connected to the write control line.

Abstract: An MOS decoder circuit including parallel rows or columns of MOS transistors connected to an input signal to be decoded. Two clocked MOS transistors of a channel type different from that used to form the rows of MOS transistors are connected as load resistances, one being connected to the drains of one row of transistors and the other being connected to an MOS transistor circuit coupled to another row of MOS transistors.

Abstract: A negative resistance device utilizing a substrate bias effect is comprised of two MOS transistors of n-channel type and p-channel type. The two transistors are connected at the sources and the gates. The drain of the n-channel MOS transistor is connected to the substrate of the p-channel MOS transistor. The drain of the p-channel MOS transistor is connected to the substrate of the n-channel MOS transistor.

Abstract: A first semiconductor region of P.sup.- type is formed in a semiconductor substrate of N.sup.- types. The N.sup.- region adjacent to the first semiconductor region is a second semiconductor region. A third semiconductor region of N.sup.+ type and a fourth semiconductor region of P.sup.+ type are formed on the first and second semiconductor regions, respectively. Between the first semiconductor region and fourth semiconductor region is formed a first channel region which includes a subregion of P.sup.- type and a fifth semiconductor region of N types. Between the second semiconductor region and third semiconductor region is formed a second channel region which includes a subregion of N.sup.- type and a sixth semiconductor region of P type. The fourth semiconductor region, the subregion of the first channel region and the sixth semiconductor region are used for a P-channel MOS transistor.

Abstract: A flip-flop circuit includes first, second, third and fourth NAND gates each with first and second output terminals. The first output terminal of the first NAND gate C and the first output terminal of the third NAND gate are connected to the input terminals of the second and fourth NAND gates, respectively. The first output terminals of the second and fourth NAND gates are connected to the input terminals of the first and third NAND gates, respectively. The second output terminals of the first and second NAND gates are connected to the input terminals of the third and fourth NAND gates, respectively. The second output terminal of the fourth NAND gate is coupled with the input terminal of the first NAND gate. A first diode is inserted between the input terminals of the first and second NAND gates and second diode is inserted between the third and fourth NAND gates.