Patents by Inventor Tetsuya Ikuta

Tetsuya Ikuta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200020828
    Abstract: Provided is a semiconductor light-emitting device which can mitigate a multipeak in an emission spectrum in a bonding-type semiconductor light-emitting device having an InP cladding layer. The semiconductor light-emitting device of the present disclosure includes a first conductive type InP cladding layer, a semiconductor light-emitting layer, and a second conductive type InP cladding layer provided sequentially over a conductive support substrate, the second conductive type InP cladding layer being on a light extraction side, and the semiconductor light-emitting device further includes a metal reflective layer, between the conductive support substrate and the first conductive type InP cladding layer, for reflecting light emitted from the semiconductor light-emitting layer; and a plurality of recesses provided in a surface of the second conductive type InP cladding layer.
    Type: Application
    Filed: December 15, 2017
    Publication date: January 16, 2020
    Applicant: DOWA Electronics Materials Co., Ltd.
    Inventors: Jumpei YAMAMOTO, Tetsuya IKUTA
  • Patent number: 10388517
    Abstract: An epitaxial substrate for an electronic device, in which a lateral direction of the substrate is defined as a main current conducting direction and a warp configuration of the epitaxial substrate is adequately controlled, as well as a method of producing the epitaxial substrate. Specifically, the epitaxial substrate for an electron device, including: a Si single crystal substrate; and a Group III nitride laminated body formed by epitaxially growing plural Group III nitride layers on the Si single crystal substrate, wherein a lateral direction of the epitaxial substrate is defined as a main current conducting direction, is characterized in that the Si single crystal substrate is a p-type substrate having a specific resistance value of not larger than 0.01 ?·cm.
    Type: Grant
    Filed: July 16, 2012
    Date of Patent: August 20, 2019
    Assignee: DOWA ELECTRONICS MATERIALS CO., LTD.
    Inventors: Tetsuya Ikuta, Jo Shimizu, Tomohiko Shibata
  • Publication number: 20190207055
    Abstract: Provided is a method of manufacturing a semiconductor optical device, which makes it possible to reduce the thickness of a semiconductor optical device including InGaAsP-based III-V compound semiconductor layers containing at least In and P to a thickness smaller than that of conventional devices, and provide a semiconductor optical device. The method of manufacturing a semiconductor optical device includes a step of forming a semiconductor laminate 30 on the InP growth substrate; a step of bonding the semiconductor laminate 30 to the support substrate 80 formed from a Si substrate, with at least the metal bonding layer 70 therebetween; and a step of removing the InP growth substrate 10.
    Type: Application
    Filed: May 30, 2017
    Publication date: July 4, 2019
    Applicant: DOWA Electronics Materials Co., Ltd.
    Inventors: Jumpei YAMAMOTO, Tetsuya IKUTA
  • Patent number: 9783195
    Abstract: A control apparatus for a vehicle includes a controller configured to (i) calculate, based on a distance and a relative speed between a host vehicle and a forward obstacle, a collision prediction time of a collision between the forward obstacle and the host vehicle; (ii) execute a predetermined control when the collision prediction time is less than or equal to a predetermined threshold, the predetermined control reducing a probability of the collision between the forward obstacle and the host vehicle, and (iii) decrease the predetermined threshold, when an accelerator pedal releasing operation is performed under a situation where the forward obstacle exists, depending on a first distance between the host vehicle and the forward obstacle at a time at which the accelerator pedal releasing operation is performed.
    Type: Grant
    Filed: January 27, 2016
    Date of Patent: October 10, 2017
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Tetsuya Ikuta, Yasutaka Matsunaga, Sho Komai, Yuma Hoshikawa
  • Publication number: 20160221574
    Abstract: A control apparatus for a vehicle includes a controller configured to (i) calculate, based on a distance and a relative speed between a host vehicle and a forward obstacle, a collision prediction time of a collision between the forward obstacle and the host vehicle; (ii) execute a predetermined control when the collision prediction time is less than or equal to a predetermined threshold, the predetermined control reducing a probability of the collision between the forward obstacle and the host vehicle, and (iii) decrease the predetermined threshold, when an accelerator pedal releasing operation is performed under a situation where the forward obstacle exists, depending on a first distance between the host vehicle and the forward obstacle at a time at which the accelerator pedal releasing operation is performed.
    Type: Application
    Filed: January 27, 2016
    Publication date: August 4, 2016
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Tetsuya IKUTA, Yasutaka MATSUNAGA, Sho KOMAI, Yuma HOSHIKAWA
  • Publication number: 20150340230
    Abstract: A III nitride epitaxial substrate with reduced warp after the formation of a main laminate and improved vertical breakdown voltage, and a method of producing the same, a III nitride epitaxial substrate includes: a Si substrate; an initial layer in contact with the Si substrate; and a superlattice laminate formed on the initial layer, the superlattice laminate including first layers made of Al?Ga1-?N (0.5<??1) and second layers made of Al?Ga1-?N (0<??0.5) that are alternately stacked, in which a composition ratio ? of the second layers gradually increases as a distance from the Si substrate increases.
    Type: Application
    Filed: November 28, 2013
    Publication date: November 26, 2015
    Inventors: Tetsuya IKUTA, Tomohiko SHIBATA
  • Patent number: 9006865
    Abstract: In heteroepitaxially growing a group-III nitride semiconductor on a Si single crystal substrate, the occurrence of cracks initiating in the wafer edge portion can be suppressed. Region A is an outermost peripheral portion outside the principal surface, being a bevel portion tapered. Regions B and C are on the same plane (the principal surface), region B (mirror-surface portion) being the center portion of the principal surface, and region C a region in the principal surface edge portion surrounding region B. The principal surface has a plane orientation, and in region B, is mirror-surface-finished. Region B occupies most of the principal surface of this Si single crystal substrate, and a semiconductor device is manufactured therein. Region C (surface-roughened portion) has a plane orientation as with region B, however, region B is mirror-surface-finished, whereas region C is surface-roughened.
    Type: Grant
    Filed: June 24, 2011
    Date of Patent: April 14, 2015
    Assignee: Dowa Electronics Materials Co., Ltd.
    Inventors: Tetsuya Ikuta, Daisuke Hino, Tomohiko Shibata
  • Patent number: 8946863
    Abstract: An epitaxial substrate for electronic devices, in which current flows in a lateral direction and of which warpage configuration is properly controlled, and a method of producing the same. The epitaxial substrate for electronic devices is produced by forming a bonded substrate by bonding a low-resistance Si single crystal substrate and a high-resistance Si single crystal substrate together; forming a buffer as an insulating layer on a surface of the bonded substrate on the high-resistance Si single crystal substrate side; and producing an epitaxial substrate by epitaxially growing a plurality of III-nitride layers on the buffer to form a main laminate. The resistivity of the low-resistance Si single crystal substrate is 100 ?·cm or less, and the resistivity of the high-resistance Si single crystal substrate is 1000 ?·cm or more.
    Type: Grant
    Filed: August 2, 2010
    Date of Patent: February 3, 2015
    Assignee: Dowa Electronics Materials Co., Ltd.
    Inventors: Tetsuya Ikuta, Daisuke Hino, Ryo Sakamoto, Tomohiko Shibata
  • Patent number: 8847203
    Abstract: A Group III nitride epitaxial laminate substrate comprising a substrate, a buffer and a main laminate in this order, wherein the buffer includes an initial growth layer, a first superlattice laminate and a second superlattice laminate in this order, the first superlattice laminate includes five to 20 sets of first AlN layers and second GaN layers, the first AlN layers and the second GaN layers being alternately stacked, and each one set of the first AlN layer and the second GaN layer has a thickness of less than 44 nm, the second superlattice laminate includes a plurality of sets of first layers made of an AlN material or an AlGaN material and second layers made of an AlGaN material having a different band gap from the first layers, the first and second layers being alternately stacked.
    Type: Grant
    Filed: November 4, 2010
    Date of Patent: September 30, 2014
    Assignee: Dowa Electronics Materials Co, Ltd.
    Inventors: Tetsuya Ikuta, Jo Shimizu, Tomohiko Shibata
  • Publication number: 20140209862
    Abstract: Provided is a Group III nitride epitaxial substrate that can suppress the occurrence of breakage during a device formation process and a method for manufacturing the same. A Group III nitride epitaxial substrate according to the present invention includes a Si substrate, an initial layer in contact with the Si substrate, and a superlattice laminate, formed on the initial layer, including a plurality of sets of laminates, each of the laminates including, in order, a first layer made of AlGaN with an Al composition ratio greater than 0.5 and 1 or less and a second layer made of AlGaN with an Al composition ratio greater than 0 and 0.5 or less. The Al composition ratio of the second layer progressively decreases with distance from the substrate.
    Type: Application
    Filed: July 11, 2012
    Publication date: July 31, 2014
    Applicant: DOWA ELECTRONICS MATERIALS CO., LTD.
    Inventors: Tetsuya Ikuta, Tomohiko Shibata
  • Patent number: 8710489
    Abstract: To provide an epitaxial substrate for electronic devices, in which current flows in a lateral direction, which enables accurate measurement of the sheet resistance of HEMTs without contact, and to provide a method of efficiently producing the epitaxial substrate for electronic devices, the method characteristically includes the steps of forming a barrier layer against impurity diffusion on one surface of a high-resistance Si-single crystal substrate, forming a buffer as an insulating layer on the other surface of the high-resistance Si-single crystal substrate, producing an epitaxial substrate by epitaxially growing a plurality of III-nitride layers on the buffer to form a main laminate, and measuring resistance of the main laminate of the epitaxial substrate without contact.
    Type: Grant
    Filed: July 13, 2010
    Date of Patent: April 29, 2014
    Assignee: Dowa Electronics Materials Co., Ltd.
    Inventors: Tetsuya Ikuta, Daisuke Hino, Ryo Sakamoto, Tomohiko Shibata
  • Patent number: 8633556
    Abstract: A method for making a solid-state imaging device includes forming a pinning layer, which is a P-type semiconductor layer or an N-type semiconductor layer, on a first substrate by deposition; forming a semiconductor layer on the pinning layer; forming a photoelectric conversion unit in the semiconductor layer, the photoelectric conversion unit being configured to convert incident light into an electrical signal; forming, on the semiconductor layer, a transistor of a pixel unit and a transistor of a peripheral circuit unit disposed in the periphery of the pixel unit, and then forming a wiring section on the semiconductor layer; bonding a second substrate on the wiring section; and removing the first substrate after the second substrate is bonded.
    Type: Grant
    Filed: January 20, 2012
    Date of Patent: January 21, 2014
    Assignee: Sony Corporation
    Inventors: Tetsuya Ikuta, Yuki Miyanami
  • Patent number: 8469760
    Abstract: A light emitting device 10 includes: a lead frame 12a serving as a mounting portion having a cup 13; a light emitting element 14, mounted on the bottom face 13a of the cup, for emitting light having a predetermined peak wavelength; a layer of large phosphor particles 16, adsorbed and formed on the light emitting element, for absorbing light emitted from the light emitting element and for emitting light having a longer peak wavelength than that of the light emitted from the light emitting element; small phosphor particles 18, which have a smaller particle diameter than that of the large phosphor particles, for absorbing at least one of light emitted from the large phosphor particles and light emitted from the light emitting element and for emitting light having a longer peak wavelength than that of the at least one of the light emitted from the large phosphor particles and the light emitted from the light emitting element; and a sealing member 20, in which the small phosphor particles are dispersed, for sealin
    Type: Grant
    Filed: March 27, 2007
    Date of Patent: June 25, 2013
    Assignee: Dowa Electronics Materials Co., Ltd.
    Inventors: Tsukasa Maruyama, Masahiro Gotoh, Tetsuya Ikuta
  • Patent number: 8426893
    Abstract: An epitaxial substrate for electronic devices is provided, which can improve vertical breakdown voltage and provides a method of producing the same. The epitaxial substrate includes a conductive SiC single crystal substrate, a buffer as an insulating layer on the SiC single crystal substrate, and a main laminate formed by epitaxially growing a plurality of Group III nitride layers on the buffer. Further, the buffer includes at least an initial growth layer in contact with the SiC single crystal substrate and a superlattice laminate having a superlattice multi-layer structure on the initial growth layer. The initial growth layer is made of a Ba1Alb1Gac1Ind1N material. Furthermore, the superlattice laminate is configured by alternately stacking a first layer made of a Ba2Alb2Gac2Ind2N material and a second layer made of a Ba3Alb3Gac3Ind3N material having a different band gap from the first layer.
    Type: Grant
    Filed: May 10, 2010
    Date of Patent: April 23, 2013
    Assignee: Dowa Electronics Materials Co., Ltd.
    Inventors: Tetsuya Ikuta, Jo Shimizu, Tomohiko Shibata, Ryo Sakamoto, Tsuneo Ito
  • Publication number: 20130087807
    Abstract: In heteroepitaxially growing a group-III nitride semiconductor on a Si single crystal substrate, the occurrence of cracks initiating in the wafer edge portion can be suppressed. Region A is an outermost peripheral portion outside the principal surface, being a bevel portion tapered. Regions B and C are on the same plane (the principal surface), region B (mirror-surface portion) being the center portion of the principal surface, and region C a region in the principal surface edge portion surrounding region B. The principal surface has a plane orientation, and in region B, is mirror-surface-finished. Region B occupies most of the principal surface of this Si single crystal substrate, and a semiconductor device is manufactured therein. Region C (surface-roughened portion) has a plane orientation as with region B, however, region B is mirror-surface-finished, whereas region C is surface-roughened.
    Type: Application
    Filed: June 24, 2011
    Publication date: April 11, 2013
    Applicant: DOWA ELECTRONICS MATERIALS CO., LTD.
    Inventors: Tetsuya Ikuta, Daisuke Hino, Tomohiko Shibata
  • Patent number: 8410472
    Abstract: An epitaxial substrate for an electronic device having a Si single crystal substrate, a buffer as an insulating layer formed on the Si single crystal substrate, and a main laminated body formed by plural group III nitride layers epitaxially grown on the buffer, wherein a lateral direction of the epitaxial substrate is defined as an electric current conducting direction. The buffer including at least an initially grown layer in contact with the Si single crystal substrate and a superlattice laminate constituted of a superlattice multilayer structure on the initially grown layer.
    Type: Grant
    Filed: December 14, 2009
    Date of Patent: April 2, 2013
    Assignee: Dowa Electronics Materials Co., Ltd.
    Inventors: Tetsuya Ikuta, Jo Shimizu, Tomohiko Shibata
  • Patent number: 8308981
    Abstract: A phosphor, which is given by a general composition formula expressed by MmAaDdOoNn:Z, (wherein element M is at least one kind of element having bivalent valency, element A is at least one kind of element having tervalent valency selected from the group consisting of Al, Ga, In, Tl, Y, Sc, P, As, Sb, and Bi, element D is Si and/or Ge, O is oxygen, N is nitrogen, and element Z is at least one kind of element selected from rare earth elements or transitional metal elements, satisfying m>0, a>0, b>0 o?0, and n=2/3 m+a+4/3b?2/3o), where a content of the element Fe is smaller than 200 ppm.
    Type: Grant
    Filed: June 18, 2010
    Date of Patent: November 13, 2012
    Assignees: Dowa Electronics Materials Co., Ltd., Nichia Corporation
    Inventors: Akira Nagatomi, Shuji Yamashita, Tetsuya Ikuta
  • Publication number: 20120273759
    Abstract: An epitaxial substrate for an electronic device, in which a lateral direction of the substrate is defined as a main current conducting direction and a warp configuration of the epitaxial substrate is adequately controlled, as well as a method of producing the epitaxial substrate. Specifically, the epitaxial substrate for an electron device, including: a Si single crystal substrate; and a Group III nitride laminated body formed by epitaxially growing plural Group III nitride layers on the Si single crystal substrate, wherein a lateral direction of the epitaxial substrate is defined as a main current conducting direction, is characterized in that the Si single crystal substrate is a p-type substrate having a specific resistance value of not larger than 0.01 ?·cm.
    Type: Application
    Filed: July 16, 2012
    Publication date: November 1, 2012
    Applicant: DOWA ELECTRONICS MATERIALS CO., LTD.
    Inventors: Tetsuya IKUTA, Jo SHIMIZU, Tomohiko SHIBATA
  • Publication number: 20120223328
    Abstract: A Group III nitride epitaxial laminate substrate comprising a substrate, a buffer and a main laminate in this order, wherein the buffer includes an initial growth layer, a first superlattice laminate and a second superlattice laminate in this order, the first superlattice laminate includes five to 20 sets of first AlN layers and second GaN layers, the first AlN layers and the second GaN layers being alternately stacked, and each one set of the first AlN layer and the second GaN layer has a thickness of less than 44 nm, the second superlattice laminate includes a plurality of sets of first layers made of an AlN material or an AlGaN material and second layers made of an AlGaN material having a different band gap from the first layers, the first and second layers being alternately stacked.
    Type: Application
    Filed: November 4, 2010
    Publication date: September 6, 2012
    Applicant: DOWA ELECTRONICS MATERIALS CO., LTD.
    Inventors: Tetsuya Ikuta, Jo Shimizu, Tomohiko Shibata
  • Patent number: 8253326
    Abstract: A light-emitting device of the present invention includes: a light-emitting element; and a phosphor layer containing phosphors that absorb light from the light-emitting element and wavelength-convert the absorbed light to emit light. The phosphor layer has a structure in which the phosphors are disposed on an applied adhesive with a thickness equal to or less than an average particle size of the phosphors. A thickness of the phosphor layer is equal to or less than five times the average particle size of the phosphors, and an occupancy ratio of the phosphors in the phosphor layer is 50% or more. Further, the phosphors disposed on the adhesive has an adjusted particle size.
    Type: Grant
    Filed: July 20, 2010
    Date of Patent: August 28, 2012
    Assignee: Dowa Electronics Materials Co., Ltd.
    Inventors: Tsukasa Maruyama, Tetsuya Ikuta