Abstract: A rectifier including an autonomous type synchronous-rectification MOSFET is provided, which prevents chattering and through-current caused by a malfunction when a noise is applied. The rectifier includes: a rectification MOSFET for performing synchronous rectification; a determination circuit configured to input a voltage between a pair of main terminals of the rectification MOSFET, and to determine whether the rectification MOSFET is in on or off state on the basis of the inputted voltage; and a gate drive circuit configured such that a gate of the rectification MOSFET is turned on and off by a comparison signal from the determination circuit, and such that a time required to boost a gate voltage when the rectification MOSFET is turned on is longer than a time required to lower the gate voltage when the rectification MOSFET is turned off.

Abstract: Provided is a semiconductor device including: a first external electrode which includes a circular outer peripheral portion; a MOSFET chip; a control circuit chip which receives voltages of a drain electrode and a source electrode of the MOSFET and supplies a signal to a gate electrode to control the MOSFET on the basis of the voltage; a second external electrode which is disposed on an opposite side of the first external electrode with respect to the MOSFET chip and includes an external terminal on a center axis of the circular outer peripheral portion of the first external electrode; and an isolation substrate which isolates the control circuit chip from the external electrode. The first external electrode, the drain electrode and the source electrode of the MOSFET chip, and the second external electrode are disposed to be overlapped in a direction of the center axis. The drain electrode of the MOSFET chip and the first external electrode are connected.

Abstract: A diode includes an anode electrode layer; a cathode electrode layer; a buffer layer of a first conductivity type formed between the anode electrode layer and the cathode electrode layer in a region extending to a location at a distance of 30 ?m or more from the cathode electrode layer; a first semiconductor layer of the first conductivity type formed in a region between the anode electrode layer and the cathode electrode layer, and being in contact with the buffer layer of the first conductivity type; and a second semiconductor layer of a second conductivity type formed in a region between the anode electrode layer and the first semiconductor layer of the first conductivity type. The carrier concentration in the first semiconductor layer is lower than the carrier concentration in the buffer layer. The carrier concentration in the buffer layer is less than 1×1015 cm?3.

Abstract: Provided is a semiconductor device including: a first external electrode which includes a circular outer peripheral portion; a MOSFET chip; a control circuit chip which receives voltages of a drain electrode and a source electrode of the MOSFET and supplies a signal to a gate electrode to control the MOSFET on the basis of the voltage; a second external electrode which is disposed on an opposite side of the first external electrode with respect to the MOSFET chip and includes an external terminal on a center axis of the circular outer peripheral portion of the first external electrode; and an isolation substrate which isolates the control circuit chip from the external electrode. The first external electrode, the drain electrode and the source electrode of the MOSFET chip, and the second external electrode are disposed to be overlapped in a direction of the center axis. The drain electrode of the MOSFET chip and the first external electrode are connected.

Abstract: Provided are a semiconductor device realized easily at low cost without requiring a complicated manufacturing process, and an alternator using the same. The semiconductor device includes a base having a base seat, a lead having a lead header, and an electronic circuit body, wherein the electronic circuit body is arranged between the base and the lead; the base seat is connected to a first surface of the electronic circuit body; the lead header is connected to a second surface of the electronic circuit body; the electronic circuit body is integrally covered by resin, including a transistor circuit chip having a switching element, a control circuit chip for controlling the switching element, a drain frame, and a source frame; either one of the drain frame and the source frame, and the base are connected; and the other one of the drain frame and the source frame, and the lead are connected.

Abstract: The rectifier includes a rectification MOSFET; a comparator having the non-inverted input terminal connected to a drain of the rectification MOSFET and the inverted input terminal connected to a source of the rectification MOSFET, and the control circuit controlling ON and OFF of the rectification MOSFET by an output of the comparator. The control circuit includes the shutoff MOSFET for performing shutoff between the drain of the rectification MOSFET and the non-inverted input terminal of the comparator and the shutoff control circuit performing electrical shutoff between the drain of the rectification MOSFET and the non-inverted input terminal of the comparator by turning off the shutoff MOSFET when a voltage of the drain of the rectification MOSFET is equal to or higher than a first predetermined voltage.

Abstract: A rectifier including an autonomous type synchronous-rectification MOSFET is provided, which prevents chattering and through-current caused by a malfunction when a noise is applied. The rectifier includes: a rectification MOSFET for performing synchronous rectification; a determination circuit configured to input a voltage between a pair of main terminals of the rectification MOSFET, and to determine whether the rectification MOSFET is in on or off state on the basis of the inputted voltage; and a gate drive circuit configured such that a gate of the rectification MOSFET is turned on and off by a comparison signal from the determination circuit, and such that a time required to boost a gate voltage when the rectification MOSFET is turned on is longer than a time required to lower the gate voltage when the rectification MOSFET is turned off.

Abstract: The semiconductor device has a first external electrode having an outer peripheral section, which has a circular shape in top plan view and which is to be attached to an alternator. On the first external electrode there mounted: a MOSFET chip; a control circuitry to which voltages at or a current flowing between a first main terminal and a second main terminal of the MOSFET chip is inputted and which generates, on the basis of the voltages or the current, a control signal applied to a gate of the MOSFET chip; and a capacitor for providing a power supply to the control circuitry. The semiconductor device further has a second external electrode disposed opposite to the first external electrode with respect to the MOSFET chip. An electrical connection is made between the first main terminal of the MOSFET chip and the first external electrode, and between the second main terminal of the MOSFET chip and the second external electrode.

Abstract: A rectifier 107 includes a rectifying MOSFET 101 that performs synchronous rectification, a control circuit 106 that inputs a voltage across a pair of a positive-side main terminal TK and a negative-side main terminal TA of the rectifying MOSFET 101 to determine an ON or OFF state of the rectifying MOSFET 101 based on the inputted voltage, and a capacitor 104 that supplies power to the control circuit 106. The control circuit 106 includes a blocking circuit 105 that inputs the voltage across the pair of main terminals of the rectifying MOSFET 101, to block power supply to the control circuit 106 when the inputted voltage across the pair of main terminals is higher than or equal to a first voltage, and to unblock power supply to the control circuit 106 when the inputted voltage across the pair of main terminals is lower than the first voltage.

Abstract: The problem addressed by the present invention is to provide a semiconductor device capable of improving dv/dt controllability via a gate drive circuit during turn-on switching. The semiconductor device comprises a plurality of trench gate groups, each trench gate group including mutually adjoining three or more trench gates, and the distance between adjoining two trench gate groups is larger than the distance between adjoining two trench gates in one trench gate group. Thereby, gate-emitter capacity increases, and therefore the semiconductor device may improve dv/dt controllability via a gate drive circuit during turn-on switching.

Abstract: It is an object of the present invention to provide a diode that can be produced with a simple method and performs a favorable recovery operation. The diode in accordance with the present invention includes a layer with a high concentration of dopants and a layer with a low concentration of dopants, and the layer with a low concentration of dopants further includes a layer with a different activation rate from other potions (see FIG. 1).

Abstract: A method and apparatus of forming a nonvolatile semiconductor device including forming a first gate insulating film on a main surface of a first semiconductor region, forming a first gate electrode on the first gate insulating film, forming a second gate insulating film, forming a second gate electrode over a first side surface of the first gate electrode, selectively removing the second gate insulating film, etching the second gate insulating film kept between the second gate electrode and a main surface of the first semiconductor region in order to form an etched charge storage layer, introducing first impurities in the first semiconductor region in a self-aligned manner to the second gate electrode in order to form a second semiconductor region, annealing the semiconductor substrate to extend the second semiconductor region to an area under the second gate electrode.

Abstract: A charge storage layer interposed between a memory gate electrode and a semiconductor substrate is formed shorter than a gate length of the memory gate electrode or a length of insulating films so as to make the overlapping amount of the charge storage layer and a source region to be less than 40 nm. Therefore, in the write state, since the movement in the transverse direction of the electrons and the holes locally existing in the charge storage layer decreases, the variation of the threshold voltage when holding a high temperature can be reduced. In addition, the effective channel length is made to be 30 nm or less so as to reduce an apparent amount of holes so that coupling of the electrons with the holes in the charge storage layer decreases; therefore, the variation of the threshold voltage when holding at room temperature can be reduced.

Abstract: A charge storage layer interposed between a memory gate electrode and a semiconductor substrate is formed shorter than a gate length of the memory gate electrode or a length of insulating films so as to make the overlapping amount of the charge storage layer and a source region to be less than 40 nm. Therefore, in the write state, since the movement in the transverse direction of the electrons and the holes locally existing in the charge storage layer decreases, the variation of the threshold voltage when holding a high temperature can be reduced. In addition, the effective channel length is made to be 30 nm or less so as to reduce an apparent amount of holes so that coupling of the electrons with the holes in the charge storage layer decreases; therefore, the variation of the threshold voltage when holding at room temperature can be reduced.

Abstract: In a split gate MONOS memory which carries out rewrite by hot carrier injection, retention characteristics are improved. A select gate electrode of a memory cell is connected to a select gate line, and a memory gate electrode is connected to a memory gate line. A drain region is connected to a bit line, and a source region is connected to a source line. Furthermore, a well line is connected to a p type well region in which the memory cell is formed. When write to the memory cell is to be carried out, write by a source side injection method is carried out while applying a negative voltage to the p type well region via the well line.

Abstract: A method of manufacturing a non-volatile semiconductor memory device is provided which overcomes a problem of penetration of implanted ions due to the difference of an optimal gate height in simultaneous formation of a self-align split gate type memory cell utilizing a side wall structure and a scaled MOS transistor. A select gate electrode to form a side wall in a memory area is formed to be higher than that of the gate electrode in a logic area so that the height of the side wall gate electrode of the self-align split gate memory cell is greater than that of the gate electrode in the logic area. Height reduction for the gate electrode is performed in the logic area before gate electrode formation.

Abstract: A diode includes: a first semiconductor layer of a first conductive type; a second semiconductor layer of a second conductive type arranged adjoining to the first semiconductor layer; a third semiconductor layer of the first conductive type arranged on a side, opposite to the second semiconductor layer, of the first semiconductor layer, and contains a dopant of the first conductive type at a higher concentration than the first semiconductor layer; a first electrode ohmically connected to the second semiconductor layer; a second electrode ohmically connected to the third semiconductor layer; and a fourth semiconductor layer arranged at a position adjoining to the third semiconductor layer between the first and third semiconductor layers, contains a dopant of a type being the same as a type of the dopant of the first conductive type contained in the third semiconductor layer, and has a carrier lifetime shorter than the third semiconductor layer.

Abstract: An operation scheme for operating stably a semiconductor nonvolatile memory device is provided. When hot-hole injection is conducted in the semiconductor nonvolatile memory device of a split gate structure, the hot-hole injection is verified using a crossing point that does not change with time. Thus, an erased state can be verified without being aware of any time-varying changes. Also, programming or programming/erasure is conducted by repeating pulse voltage or multi-step voltage application to a gate section multiple times.

Abstract: A charge storage layer interposed between a memory gate electrode and a semiconductor substrate is formed shorter than a gate length of the memory gate electrode or a length of insulating films so as to make the overlapping amount of the charge storage layer and a source region to be less than 40 nm. Therefore, in the write state, since the movement in the transverse direction of the electrons and the holes locally existing in the charge storage layer decreases, the variation of the threshold voltage when holding a high temperature can be reduced. In addition, the effective channel length is made to be 30 nm or less so as to reduce an apparent amount of holes so that coupling of the electrons with the holes in the charge storage layer decreases; therefore, the variation of the threshold voltage when holding at room temperature can be reduced.

Abstract: A charge storage layer interposed between a memory gate electrode and a semiconductor substrate is formed shorter than a gate length of the memory gate electrode or a length of insulating films so as to make the overlapping amount of the charge storage layer and a source region to be less than 40 nm. Therefore, in the write state, since the movement in the transverse direction of the electrons and the holes locally existing in the charge storage layer decreases, the variation of the threshold voltage when holding a high temperature can be reduced. In addition, the effective channel length is made to be 30 nm or less so as to reduce an apparent amount of holes so that coupling of the electrons with the holes in the charge storage layer decreases; therefore, the variation of the threshold voltage when holding at room temperature can be reduced.