Patents by Inventor Tetsuya Shibayama

Tetsuya Shibayama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11606552
    Abstract: A video encoding device includes a local decode generation unit for generating a reference image based on a result of encoding of a divided image, a compression unit for compressing the reference image to generate a compressed data, a reference image storage determination unit for determining whether to store the compressed data in a memory, and an inter-prediction unit for performing motion vector search for inter-coding based on a reference image stored in the memory. The reference image storage determination unit sets an allowable data amount used for storing the reference image for each determined area of the moving image data, and determines whether or not to store the compressed data obtained by compressing the reference image in the memory based on the allowable data amount. Inter-prediction unit sets the reference image corresponding to the compressed data stored in the memory as the search range of motion vector search.
    Type: Grant
    Filed: July 20, 2021
    Date of Patent: March 14, 2023
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Maiki Hosokawa, Toshiyuki Kaya, Tetsuya Shibayama, Seiji Mochizuki, Tomohiro Une, Kazushi Akie
  • Publication number: 20220138919
    Abstract: An image processing device and image processing methods that improve image quality by reducing latency and improving the performance of local processing are provided. An image processing device using an image input signal as an input and an image output signal as an output includes a first image processing unit and a second image processing unit. The first image processing unit includes a histogram processing unit for extracting image characteristic data from the image input signal, a first image parameter processing unit for creating a first parameter group for performing image processing from the image characteristic data, and an arithmetic processing unit for processing the image input signal to create an image output signal. The second image processing unit has a second image parameter processing unit for creating a second parameter group for performing image processing from the image characteristic data.
    Type: Application
    Filed: November 4, 2020
    Publication date: May 5, 2022
    Inventors: Quyet Hoang, Hai NGUYEN, Son LE, Kenichi IWATA, Tetsuya SHIBAYAMA
  • Publication number: 20210352278
    Abstract: A video encoding device includes a local decode generation unit for generating a reference image based on a result of encoding of a divided image, a compression unit for compressing the reference image to generate a compressed data, a reference image storage determination unit for determining whether to store the compressed data in a memory, and an inter-prediction unit for performing motion vector search for inter-coding based on a reference image stored in the memory. The reference image storage determination unit sets an allowable data amount used for storing the reference image for each determined area of the moving image data, and determines whether or not to store the compressed data obtained by compressing the reference image in the memory based on the allowable data amount. Inter-prediction unit sets the reference image corresponding to the compressed data stored in the memory as the search range of motion vector search.
    Type: Application
    Filed: July 20, 2021
    Publication date: November 11, 2021
    Inventors: Maiki HOSOKAWA, Toshiyuki KAYA, Tetsuya SHIBAYAMA, Seiji MOCHIZUKI, Tomohiro UNE, Kazushi AKIE
  • Publication number: 20210294691
    Abstract: In a data processing device comprising a memory controller controlling writing/reading of data to/from the memory, a processor requesting writing/reading of data, and an error detection module requesting writing/reading of data to/from the memory controller in accordance with a request from the processor, an error detection module calculates a first error detection code of the first data having a write request from the processor, reads the second data having a read request from the processor from the memory, calculates a second error detection code from the read data, compares the first error detection code and the second error detection code, and transmits the result of the comparison to the external module.
    Type: Application
    Filed: March 17, 2020
    Publication date: September 23, 2021
    Inventors: Katsushige MATSUBARA, Ryoji HASHIMOTO, Takahiro IRITA, Kenichi SHIMADA, Tetsuya SHIBAYAMA
  • Patent number: 11102475
    Abstract: A video encoding device includes a local decode generation unit for generating a reference image based on a result of encoding of a divided image, a compression unit for compressing the reference image to generate a compressed data, a reference image storage determination unit for determining whether to store the compressed data in a memory, and an inter-prediction unit for performing motion vector search for inter-coding based on a reference image stored in the memory. The reference image storage determination unit sets an allowable data amount used for storing the reference image for each determined area of the moving image data, and determines whether or not to store the compressed data obtained by compressing the reference image in the memory based on the allowable data amount. Inter-prediction unit sets the reference image corresponding to the compressed data stored in the memory as the search range of motion vector search.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: August 24, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Maiki Hosokawa, Toshiyuki Kaya, Tetsuya Shibayama, Seiji Mochizuki, Tomohiro Une, Kazushi Akie
  • Publication number: 20210132978
    Abstract: In a virtualization system that includes a hypervisor that performs OSID management for linking a plurality of OSs with resources, a guest OS that receives an initial value from the hypervisor and sets a OSID for each resource, and a OSID manager that sets a OSID for each resource, a new OSID created by OSID generator in OSID manager after a certain period of time has elapsed after setting the initial value is set to the guest OS and the IP (resource), and is requested to be updated to a new OSID set by the update controller in OSID manager. This enables simultaneous updating of OSID of the guest operating system and the resources, thus achieving high robustness.
    Type: Application
    Filed: October 6, 2020
    Publication date: May 6, 2021
    Inventors: Tetsuya SHIBAYAMA, Nhat Van HUYNH, Katsushige MATSUBARA, Seiji MOCHIZUKI
  • Publication number: 20210136387
    Abstract: A video image encoding device includes: an image encoding unit that performs predictive encoding by obtaining a difference between a divided image included in a frame as a target of predictive encoding and a prediction image; local decode generation unit that decodes an encoding result of the divided image by the image encoding unit to generate a reference image; a first buffer that stores pixel data generated by the local decode generation unit; a compression unit that refers to the first buffer to compress the reference image and generates compressed data; an allowable data amount setting unit that presets an allowable data amount to be stored in the memory for each predetermined area of the frame as the target of the predictive encoding; and a reference image storage determination unit that determines whether the compressed data is store in the memory based on the allowable data amount, and stores the compressed data in the memory based on a determination result of storing the compressed data in the memory
    Type: Application
    Filed: October 21, 2020
    Publication date: May 6, 2021
    Inventors: Hung Van Cao, Toshiyuki Kaya, Tetsuya Shibayama
  • Patent number: 10986373
    Abstract: An image encoding device includes an encoding circuit configured to encode an image, the image being constituted of a plurality of columns and a plurality of rows of which width are longer than the columns, generate a reference image and stores the reference image into a memory, and output a bit stream including the encoded image. The image encoding device also includes an image rotation circuit configured to rotate the image read from the memory by 90° and output the rotated image to a encoding processing circuit, and a read address generating circuit configured to read the column of the image from the memory, and provide the column with the image rotation circuit.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: April 20, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Seiji Mochizuki, Kazushi Akie, Tetsuya Shibayama, Kenichi Iwata
  • Publication number: 20200195918
    Abstract: A video encoding device includes a local decode generation unit for generating a reference image based on a result of encoding of a divided image, a compression unit for compressing the reference image to generate a compressed data, a reference image storage determination unit for determining whether to store the compressed data in a memory, and an inter-prediction unit for performing motion vector search for inter-coding based on a reference image stored in the memory. The reference image storage determination unit sets an allowable data amount used for storing the reference image for each determined area of the moving image data, and determines whether or not to store the compressed data obtained by compressing the reference image in the memory based on the allowable data amount. Inter-prediction unit sets the reference image corresponding to the compressed data stored in the memory as the search range of motion vector search.
    Type: Application
    Filed: October 24, 2019
    Publication date: June 18, 2020
    Inventors: Maiki HOSOKAWA, Toshiyuki KAYA, Tetsuya SHIBAYAMA, Seiji MOCHIZUKI, Tomohiro UNE, Kazushi AKIE
  • Patent number: 10638148
    Abstract: A video encoding/decoding system includes a video encoding device, and a video decoding device. The video encoding device includes an encoding circuit for encoding an image including a diagnostic image or a normal image. The video decoding device includes a decoding circuit for decoding the image encoded in the encoding circuit, a check signal generation circuit for generating a check signal of the decoded image, a storage circuit for storing the check signal generated by the check signal generation circuit, and a comparison circuit for comparing the check signal stored in the storage circuit with the check signal generated by the check signal generation circuit. The failure is detected by comparing the check signal including an expected value stored in the storage circuit with the check signal including a comparison value generated by the check signal generation circuit by processing the same image data a plurality of times.
    Type: Grant
    Filed: August 2, 2018
    Date of Patent: April 28, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Seiji Mochizuki, Toshiyuki Kaya, Hiroshi Ueda, Tetsuya Shibayama
  • Patent number: 10587888
    Abstract: A video encoding/decoding system includes a video encoding device, and a video decoding device. The video encoding device includes an encoding circuit for encoding an image including a diagnostic image or a normal image. The video decoding device includes a decoding circuit for decoding the image encoded in the encoding circuit, a check signal generation circuit for generating a check signal of the decoded image, a storage circuit for storing the check signal generated by the check signal generation circuit, and a comparison circuit for comparing the check signal stored in the storage circuit with the check signal generated by the check signal generation circuit. The failure is detected by comparing the check signal including an expected value stored in the storage circuit with the check signal including a comparison value generated by the check signal generation circuit by processing the same image data a plurality of times.
    Type: Grant
    Filed: August 2, 2018
    Date of Patent: March 10, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Seiji Mochizuki, Toshiyuki Kaya, Hiroshi Ueda, Tetsuya Shibayama
  • Publication number: 20200005353
    Abstract: The present invention provides a service car in which the effect of advertisement is increased and the convenience for users is increased. The processing executed by the CPU of the moving object as the service car includes the steps of obtaining an advertisement from the server (S505), displaying the advertisement on a monitor outside the moving object (S510), accepting input of each signal output from an external information acquisition device (camera, microphone, sensor) provided in the moving object (S520), obtaining external information representing the periphery of the moving object and storing the information (S530), obtaining the travel information of the moving object (S540), estimating the effect of the advertisement based on the external information and the travel information (S550), determining a reward for the advertisement based on a predetermined reward criterion and the effect (S560), and calculating a usage fee for the moving object based on the determined reward.
    Type: Application
    Filed: June 20, 2019
    Publication date: January 2, 2020
    Inventors: Tetsuya SHIBAYAMA, Seiji MOCHIZUKI, Nhat Van HUYNH, Hiroshi UEDA, Toshiyuki KAYA
  • Patent number: 10419663
    Abstract: A semiconductor device includes: an encoding processing unit that stores an encoded stream of an input data that is encoded based on the specified encoding control information; a buffer management unit that calculates the transmission buffer occupancy indicating the amount of data stored in a transmission buffer according to the generated data amount, and the reception buffer occupancy indicating the amount of data stored in a reception buffer, which is the destination of the encoded stream; and a control information specifying unit that, when the transmission buffer occupancy is equal to or less than a first threshold, specifies the encoding control information based on the reception buffer occupancy, and when the transmission buffer occupancy is greater than the first threshold, specifies the encoding control information to further reduce the generated data amount than in the case of equal to or less than the first threshold, to the encoding processing unit.
    Type: Grant
    Filed: February 1, 2017
    Date of Patent: September 17, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Tetsuya Shibayama, Toshiyuki Kaya, Seiji Mochizuki, Ryoji Hashimoto
  • Patent number: 10362306
    Abstract: Included are an encoding section, a decoding section, and an image recognition section. The encoding section performs an encoding process for a video signal to be input based on a calculated encoding mode, and transmits an encoded stream. The decoding section performs a decoding process for the received encoded stream, and outputs a decoded image. The image recognition section performs an image recognition process for the decoded image. The encoding section adjusts the encoding mode based on recognition accuracy information representing the certainty of a recognition result in the image recognition section.
    Type: Grant
    Filed: August 19, 2015
    Date of Patent: July 23, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Tetsuya Shibayama, Seiji Mochizuki, Katsushige Matsubara, Kenichi Iwata
  • Patent number: 10334262
    Abstract: The present invention is directed to reduce deterioration in parallel processing capability. In a moving-picture decoding processing apparatus, information of a first plurality of frames and a second plurality of frames is supplied from a decoding control unit to first and second decoding processing units. For decoding the information from an intermediate point to an end point of a second preceding frame by the second decoding unit in a third period, use of a result of the process of the first decoding processing unit in the third period is inhibited, and use of a result of the process of a first preceding frame by the first decoding processing unit in a second period is permitted by an end signal.
    Type: Grant
    Filed: October 20, 2014
    Date of Patent: June 25, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Katsushige Matsubara, Seiji Mochizuki, Toshiyuki Kaya, Tetsuya Shibayama
  • Patent number: 10225563
    Abstract: Making effective use of an image encoder and an image decoder for processing a color image of a general-purpose standard bit depth, an image transmission device capable of transmitting/receiving a monochrome image of a higher bit depth is configured. An image transmission device includes an image encoder to encode a high bit-depth monochrome image and output encoded data and an image decoder to generate, by decoding the encoded data received via a transmission path, a high bit-depth monochrome image. The image encoder decomposes the input high bit-depth image data into plural bit planes corresponding to color image data of a standard bit depth and encodes the standard bit-depth color image data. The image decoder decodes the color image data of the standard bit depth and synthesizes, from the decoded standard bit-depth color image data, a high bit-depth monochrome image.
    Type: Grant
    Filed: July 9, 2016
    Date of Patent: March 5, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Tomohiro Une, Takahiko Sugimoto, Kwangsoo Park, Toshiyuki Kaya, Tetsuya Shibayama, Seiji Mochizuki
  • Patent number: 10158869
    Abstract: A video decoding processing apparatus which can reduce overhead for the start of parallel decoding processing. The video decoding processing apparatus includes a parsing unit, and first and second video processing units. A coding bit stream including information of largest coding units each having at least a prescribed pixel size is supplied to an input terminal of the parsing unit. The parsing unit performs parsing of the syntax of the coding bit stream to thereby generate parallel-processable first and second intermediate streams from the largest coding unit. The first and second video processing units parallel-process the first and second intermediate streams generated from the parsing unit.
    Type: Grant
    Filed: October 2, 2014
    Date of Patent: December 18, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Tetsuya Shibayama, Seiji Mochizuki, Kenichi Iwata, Motoki Kimura
  • Publication number: 20180343461
    Abstract: A video encoding/decoding system includes a video encoding device, and a video decoding device. The video encoding device includes an encoding circuit for encoding an image including a diagnostic image or a normal image. The video decoding device includes a decoding circuit for decoding the image encoded in the encoding circuit, a check signal generation circuit for generating a check signal of the decoded image, a storage circuit for storing the check signal generated by the check signal generation circuit, and a comparison circuit for comparing the check signal stored in the storage circuit with the check signal generated by the check signal generation circuit. The failure is detected by comparing the check signal including an expected value stored in the storage circuit with the check signal including a comparison value generated by the check signal generation circuit by processing the same image data a plurality of times.
    Type: Application
    Filed: August 2, 2018
    Publication date: November 29, 2018
    Inventors: Seiji MOCHIZUKI, Toshiyuki KAYA, Hiroshi UEDA, Tetsuya SHIBAYAMA
  • Patent number: 10123022
    Abstract: In a picture encoding device and a picture decoding device, the access to a reference frame memory is suppressed. The picture encoding device is comprised of a first encoder for intra picture encoding, a second encoder for inter picture encoding, and an intermediate buffer. A local decoded picture generated by the first encoder is stored as a reference picture in the intermediate buffer, and the inter picture encoding by the second encoder is performed by referring to the local decoded picture in the intermediate buffer. A picture decoding device is comprised of a first decoder for intra picture decoding, a second decoder for inter picture decoding, and an intermediate buffer. A local decoded picture generated by the first decoder is stored as a reference picture in the intermediate buffer, and the inter picture decoding by the second decoder is performed by referring the local decoded picture in the intermediate buffer.
    Type: Grant
    Filed: June 24, 2015
    Date of Patent: November 6, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Toshiyuki Kaya, Seiji Mochizuki, Tetsuya Shibayama, Kenichi Iwata, Hiroshi Ueda, Ren Imaoka
  • Patent number: 10051280
    Abstract: A video encoding/decoding system includes a video encoding device and a video decoding device. The video encoding device includes an encoding part for encoding a diagnostic image or normal image. The video decoding device includes a decoding part for decoding the image encoded by the encoding part, a check signal generation part for generating a check signal of the decoded image, a storage part for storing the expected value of the check signal of the diagnostic image or the check signal generated by the check signal generation part, and a comparison part for comparing the check signal stored in the storage part with the check signal generated by the check signal generation part, in order to detect failure in all the paths from the image input part of the video encoding device to the image output part of the video decoding device.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: August 14, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Seiji Mochizuki, Toshiyuki Kaya, Hiroshi Ueda, Tetsuya Shibayama