Patents by Inventor Tetsuya Takeuchi

Tetsuya Takeuchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250151463
    Abstract: The semiconductor light-emitting device includes a base layer including an n-type semiconductor layer, a tunnel junction part on the n-type semiconductor layer, and a p-type semiconductor layer on the tunnel junction part, a plurality of columnar semiconductors on the base layer, a buried layer filling in a space between each of the plurality of columnar semiconductors, and a current suppression region suppressing a current, where each of the plurality of columnar semiconductors has a hexagonal column, and an active layer covering the hexagonal column, where the hexagonal column has a hexagonal first surface and a second surface opposite to the first surface, where the first surface faces the base layer, where the second surface faces the current suppression region, where the buried layer is an n-type semiconductor, and where the hexagonal column is a p-type semiconductor.
    Type: Application
    Filed: January 13, 2025
    Publication date: May 8, 2025
    Inventors: Koji OKUNO, Koichi MIZUTANI, Masaki OYA, Kazuyoshi IIDA, Satoshi KAMIYAMA, Tetsuya TAKEUCHI, Motoaki IWAYA, Isamu AKASAKI
  • Publication number: 20250122643
    Abstract: A method for producing a Group III nitride semiconductor, includes: performing an ammonia treatment of supplying a gas containing ammonia to a surface of a substrate containing sapphire; subjecting the surface of the substrate to a heat treatment in a hydrogen-dominated atmosphere, after the ammonia treatment; nitriding the surface of the substrate by supplying a gas containing ammonia to the surface of the substrate, after the subjecting; and forming a crystal nucleus layer on the substrate by generating nuclei of GaN, AlGaN or AlN on the substrate, after the nitriding.
    Type: Application
    Filed: October 9, 2024
    Publication date: April 17, 2025
    Inventors: Koji OKUNO, Yoshiki SAITO, Tetsuya TAKEUCHI, Satoshi KAMIYAMA, Motoaki IWAYA, Hisanori ISHIGURO, Tomoaki KACHI
  • Publication number: 20240421259
    Abstract: A light emitting device includes: a flip-chip type light emitting element; a sealing portion; and a lens as defined herein, the light emitting element includes an n-type layer, an active layer, an electron blocking layer, a composition gradient layer, a p-type contact layer, and a p-side electrode as defined herein, and a thickness of the composition gradient layer is set such that light directed from the active layer toward the n-type layer and light directed from the active layer toward a side opposite to the n-type layer and then reflected by the p-side electrode toward the n-type layer strengthen each other in a direction perpendicular to a main surface of the light emitting element due to interference.
    Type: Application
    Filed: June 13, 2024
    Publication date: December 19, 2024
    Inventors: Koji OKUNO, Yoshiki SAITO, Masaki OYA, Kengo NAGATA, Tetsuya TAKEUCHI, Satoshi KAMIYAMA, Motoaki IWAYA, Hisanori ISHIGURO, Rie IWATSUKI
  • Publication number: 20240380173
    Abstract: A surface emitting laser includes a gallium-nitride-based semiconductor substrate, a first multilayer reflector, a semiconductor structure layer including an active layer, a first electrode layer, a second electrode layer formed on an upper surface of the semiconductor structure layer and electrically in contact with a semiconductor layer of the semiconductor structure layer in one region of the upper surface, and a second multilayer reflector configuring a resonator between the first multilayer reflector and the second multilayer reflector. An upper surface of the semiconductor substrate is a surface offset from a c-plane to any one of crystal planes of an m-plane—or an a-plane. The one region has a shape having a longitudinal direction in an m-axis direction when the upper surface is offset to the m-plane, and a shape having a longitudinal direction in an a-axis direction when the upper surface is offset to the a-plane.
    Type: Application
    Filed: August 4, 2022
    Publication date: November 14, 2024
    Applicants: MEIJO UNIVERSITY, STANLEY ELECTRIC CO., LTD.
    Inventors: Tetsuya TAKEUCHI, Masaru KURAMOTO
  • Publication number: 20240113174
    Abstract: A laminate includes an amorphous glass substrate, and an AlN layer formed on the amorphous glass substrate. The AlN layer is c-axis oriented on the amorphous glass substrate, a glass transition temperature (Tg) of the amorphous glass substrate is 720° C. to 810° C., a coefficient of thermal expansion (CTE) of the amorphous glass substrate is 3.5×10?6 [1/K] to 4.0×10?6 [1/K], and a softening point of the amorphous glass substrate is 950° C. to 1050° C.
    Type: Application
    Filed: December 7, 2023
    Publication date: April 4, 2024
    Applicants: Japan Display Inc., MEIJO UNIVERSITY
    Inventors: Masanobu IKEDA, Arichika ISHIDA, Satoshi KAMIYAMA, Motoaki IWAYA, Tetsuya TAKEUCHI
  • Publication number: 20240106189
    Abstract: A chip on submount includes: a submount including a first surface directed in a first direction; a covering layer mounted on the first surface, extending to intersect the first direction, and including a second surface directed in the first direction; a laser element mounted on the second surface and including: a third surface directed in the first direction; and a light emission unit positioned at an intermediate portion of the laser element along a second direction intersecting the first direction, extending in a third direction intersecting the first direction and second direction, and configured to output laser light in the third direction; and a bonding wire attached onto the third surface and configured to exert a pressing force on the laser element, the pressing force including a component force directed in a direction opposite to the first direction.
    Type: Application
    Filed: December 11, 2023
    Publication date: March 28, 2024
    Applicant: FURUKAWA ELECTRIC CO., LTD.
    Inventors: Yasumasa KAWAKITA, Masakazu MIURA, Hirotatsu ISHII, Tetsuya TAKEUCHI
  • Patent number: 11916164
    Abstract: A method for manufacturing a light-emitting element includes providing the light-emitting element that includes a light-emitting layer with an emission wavelength of not more than 306 nm and a p-type layer including AlGaInN including Mg as an acceptor, and removing hydrogen in the p-type layer from the light-emitting element by irradiating the light-emitting element with ultraviolet light at a wavelength of not more than 306 nm from outside and treating the light-emitting element with heat in a state in which a reverse voltage, or a forward voltage lower than a threshold voltage of the light-emitting element, or no voltage is applied to the light-emitting element. The removing of hydrogen in the p-type layer from the light-emitting element is performed in a N2 atmosphere at not less than 650° C. or in a N2+O2 atmosphere at not less than 500° C.
    Type: Grant
    Filed: December 29, 2021
    Date of Patent: February 27, 2024
    Assignees: TOYODA GOSEI CO., LTD., MEIJO UNIVERSITY
    Inventors: Yoshiki Saito, Shinya Boyama, Shinichi Matsui, Hiroshi Miwa, Kengo Nagata, Tetsuya Takeuchi, Hisanori Ishiguro
  • Publication number: 20230369534
    Abstract: A semiconductor light emitting element includes: a growth substrate; a mask formed on the growth substrate; and a columnar semiconductor layer grown from at least one opening that is provided in the mask. The columnar semiconductor layer includes an n-type nanowire layer formed at a center thereof, an active layer formed on an outer periphery of the n-type nanowire layer, and a p-type semiconductor layer formed on an outer periphery of the active layer. An opening ratio of the opening is 0.1% or more and 5.0% or less, and a light emission wavelength is 480 nm or more.
    Type: Application
    Filed: August 25, 2021
    Publication date: November 16, 2023
    Applicants: KOITO MANUFACTURING CO., LTD., MEIJO UNIVERSITY
    Inventors: Satoshi KAMIYAMA, Tetsuya TAKEUCHI, Motoaki lWAYA, Isamu AKASAKI, Weifang LU, Kazuma ITO, Naoki SONE
  • Patent number: 11462659
    Abstract: Provided is a semiconductor light emitting device including a growth substrate; a pillar-shaped semiconductor layer formed on the growth substrate; and a buried semiconductor layer formed to cover the pillar-shaped semiconductor layer, wherein the pillar-shaped semiconductor layer has an n-type nanowire layer formed at a center, an active layer formed on an outermore side than the n-type nanowire layer, a p-type semiconductor layer formed on an outermore side than the active layer and a tunnel junction layer formed on an outermore side than the p-type semiconductor layer, and wherein at least a part of the pillar-shaped semiconductor layer is provided with a removed region formed by removing from the buried semiconductor layer to a part of the tunnel junction layer.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: October 4, 2022
    Assignees: KOITO MANUFACTURING CO., LTD., MEIJO UNIVERSITY, TOYODA GOSEI CO., LTD.
    Inventors: Satoshi Kamiyama, Tetsuya Takeuchi, Motoaki Iwaya, Isamu Akasaki, Lu Weifang, Naoki Sone, Kazuyoshi Iida, Ryo Nakamura, Masaki Oya
  • Publication number: 20220246789
    Abstract: A buried layer forming step includes three steps of a facet structure forming step, a c-plane forming step, and a flattening step. In the facet structure forming step, a buried layer grows to form a periodic facet structure that matches an arrangement pattern of columnar semiconductors. In the c-plane forming step, the buried layer grows such that a {0001} plane (upper surface) is formed in a region of the buried layer corresponding to an upper portion of the columnar semiconductor. In the flattening step, lateral growth of the buried layer is promoted and the c-plane formed in the c-plane forming step is widened to flatten a surface of the buried layer.
    Type: Application
    Filed: January 28, 2022
    Publication date: August 4, 2022
    Inventors: Koji OKUNO, Koichi MIZUTANI, Masaki OYA, Kazuyoshi IIDA, Naoki SONE, Satoshi KAMIYAMA, Tetsuya TAKEUCHI, Motoaki IWAYA, Isamu AKASAKI
  • Publication number: 20220246793
    Abstract: To suppress current leakage between the semiconductor layer below the mask and the buried layer above the mask. To reduce the drive voltage and improve the emission efficiency by improving the efficiency of carrier injection into the active layer. The semiconductor light-emitting device includes a substrate, a mask, a columnar semiconductor, a buried layer, a cathode electrode, and an anode electrode. The substrate has a conductive substrate, an n-type semiconductor layer disposed on the conductive substrate, and a p-type semiconductor layer disposed on the n-type semiconductor layer. The p-type semiconductor layer has a high resistance, thereby enhancing insulation between the n-type semiconductor layer and the buried layer.
    Type: Application
    Filed: January 21, 2022
    Publication date: August 4, 2022
    Inventors: Koji OKUNO, Koichi MIZUTANI, Masaki OYA, Kazuyoshi IIDA, Satoshi KAMIYAMA, Tetsuya TAKEUCHI, Motoaki IWAYA, Isamu AKASAKI
  • Publication number: 20220231189
    Abstract: A method for manufacturing a light-emitting element includes providing the light-emitting element that includes a light-emitting layer with an emission wavelength of not more than 306 nm and a p-type layer including AlGaInN including Mg as an acceptor, and removing hydrogen in the p-type layer from the light-emitting element by irradiating the light-emitting element with ultraviolet light at a wavelength of not more than 306 nm from outside and treating the light-emitting element with heat in a state in which a reverse voltage, or a forward voltage lower than a threshold voltage of the light-emitting element, or no voltage is applied to the light-emitting element. The removing of hydrogen in the p-type layer from the light-emitting element is performed in a N2 atmosphere at not less than 650° C. or in a N2+O2 atmosphere at not less than 500° C.
    Type: Application
    Filed: December 29, 2021
    Publication date: July 21, 2022
    Inventors: Yoshiki Saito, Shinya Boyama, Shinichi Matsui, Hiroshi Miwa, Kengo Nagata, Tetsuya Takeuchi, Hisanori Ishiguro
  • Patent number: 11146040
    Abstract: Included is a semiconductor multilayer film in which a non-doped InAlN layer and a GaN layer formed on said InAlN layer and containing a dopant are stacked a plurality of times.
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: October 12, 2021
    Assignees: MEIJO UNIVERSITY, STANLEY ELECTRIC CO., LTD.
    Inventors: Tetsuya Takeuchi, Isamu Akasaki, Kazuki Kiyohara, Masaru Takizawa, Ji-Hao Liang
  • Publication number: 20210111538
    Abstract: Included is a semiconductor multilayer film in which a non-doped InAlN layer and a GaN layer formed on said InAlN layer and containing a dopant are stacked a plurality of times.
    Type: Application
    Filed: March 13, 2018
    Publication date: April 15, 2021
    Applicants: MEIJO UNIVERSITY, STANLEY ELECTRIC CO., LTD.
    Inventors: Tetsuya TAKEUCHI, Isamu AKASAKI, Kazuki KIYOHARA, Masaru TAKIZAWA, Ji-Hao LIANG
  • Publication number: 20210074877
    Abstract: Provided is a semiconductor light emitting device including a growth substrate; a pillar-shaped semiconductor layer formed on the growth substrate; and a buried semiconductor layer formed to cover the pillar-shaped semiconductor layer, wherein the pillar-shaped semiconductor layer has an n-type nanowire layer formed at a center, an active layer formed on an outermore side than the n-type nanowire layer, a p-type semiconductor layer formed on an outermore side than the active layer and a tunnel junction layer formed on an outermore side than the p-type semiconductor layer, and wherein at least a part of the pillar-shaped semiconductor layer is provided with a removed region formed by removing from the buried semiconductor layer to a part of the tunnel junction layer.
    Type: Application
    Filed: September 9, 2020
    Publication date: March 11, 2021
    Applicants: KOITO MANUFACTURING CO., LTD., MEIJO UNIVERSITY, TOYODA GOSEI CO., LTD.
    Inventors: Satoshi Kamiyama, Tetsuya Takeuchi, Motoaki Iwaya, Isamu Akasaki, Lu Weifang, Naoki Sone, Kazuyoshi Iida, Ryo Nakamura, Masaki Oya
  • Patent number: 10892601
    Abstract: A vertical cavity light-emitting element comprises a substrate, a first multilayer reflector formed on the substrate, a semiconductor structure layer formed on the first multilayer reflector and including a light emitting layer, a second multilayer reflector formed on the semiconductor structure layer and constituting a resonator together with the first multilayer reflector, and a light guide layer configured to form a light guide structure including a center region extending in a direction perpendicular to the upper surface of said substrate between the first and second multilayer reflectors and including a light emission center of the light-emitting layer and a peripheral region provided around the center region and having a smaller optical distance between the first and second multilayer reflectors than that in the center region. The second multilayer reflector has a flatness property over the center region and the peripheral region.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: January 12, 2021
    Assignees: STANLEY ELECTRIC CO., LTD., MEIJO UNIVERSITY
    Inventors: Masaru Kuramoto, Seiichiro Kobayashi, Tetsuya Takeuchi
  • Patent number: 10833223
    Abstract: To provide a Group III nitride semiconductor light-emitting device exhibiting the improved light extraction efficiency as well as reducing the influence of polarization that a p-type conductivity portion and an n-type conductivity portion occur in the AlGaN layer caused by the Al composition variation, and a production method therefor. A first p-type contact layer is a p-type AlGaN layer. A second p-type contact layer is a p-type AlGaN layer. The Al composition in the first p-type contact layer is reduced with distance from a light-emitting layer. The Al composition in the second p-type contact layer is reduced with distance from the light-emitting layer. The Al composition in the second p-type contact layer is lower than that in the first p-type contact layer. The Al composition variation rate to the unit thickness in the second p-type contact layer is higher than that in the first p-type contact layer.
    Type: Grant
    Filed: November 8, 2018
    Date of Patent: November 10, 2020
    Assignees: TOYODA GOSEI CO., LTD., MEIJO UNIVERSITY
    Inventors: Tetsuya Takeuchi, Satoshi Kamiyama, Motoaki Iwaya, Isamu Akasaki, Hisanori Kojima, Toshiki Yasuda, Kazuyoshi Iida
  • Publication number: 20200144451
    Abstract: Fabricating a high-quality nitride semiconductor crystal at a lower temperature. A nitride semiconductor crystal is fabricated by supplying onto a substrate (105) a group III element and/or a compound thereof, a nitrogen element and/or a compound thereof and an Sb element and/or a compound thereof, all of which serve as materials, and thereby vapor-growing at least one layer of nitride semiconductor film (104). A supply ratio of the Sb element to the nitrogen element in a growth process of the at least one layer of the nitride semiconductor film (104) is set to not less than 0.004.
    Type: Application
    Filed: January 9, 2020
    Publication date: May 7, 2020
    Applicant: MEIJO UNIVERSITY
    Inventors: Tetsuya TAKEUCHI, Tomoyuki SUZUKI, Hiroki SASAJIMA, Motoaki IWAYA, Isamu AKASAKI
  • Patent number: 10593831
    Abstract: Achieving resistance reduction of a nitride semiconductor multilayer film reflector. In the nitride semiconductor multilayer film reflector, a first semiconductor layer has a higher Al composition than a second semiconductor layer. A first composition-graded layer is interposed between the first and second semiconductor layers so as to be located at a group III element face side of the first semiconductor layer, the first composition-graded layer being adjusted so that its Al composition becomes lower as coming close to the second semiconductor layer. A second composition-graded layer is interposed between the first and second semiconductor layers so as to be located at a nitride face side of the first semiconductor layer. The second composition-graded layer is adjusted so that its Al composition becomes lower as coming close to the second semiconductor layer.
    Type: Grant
    Filed: March 19, 2014
    Date of Patent: March 17, 2020
    Assignee: MEIJO UNIVERSITY
    Inventors: Tetsuya Takeuchi, Motoaki Iwaya, Isamu Akasaki
  • Publication number: 20190363515
    Abstract: A vertical cavity light-emitting element comprises a substrate, a first multilayer reflector formed on the substrate, a semiconductor structure layer formed on the first multilayer reflector and including a light emitting layer, a second multilayer reflector formed on the semiconductor structure layer and constituting a resonator together with the first multilayer reflector, and a light guide layer configured to form a light guide structure including a center region extending in a direction perpendicular to the upper surface of said substrate between the first and second multilayer reflectors and including a light emission center of the light-emitting layer and a peripheral region provided around the center region and having a smaller optical distance between the first and second multilayer reflectors than that in the center region. The second multilayer reflector has a flatness property over the center region and the peripheral region.
    Type: Application
    Filed: May 22, 2019
    Publication date: November 28, 2019
    Applicants: STANLEY ELECTRIC CO., LTD., MEIJO UNIVERSITY
    Inventors: Masaru KURAMOTO, Seiichiro KOBAYASHI, Tetsuya TAKEUCHI