Patents by Inventor Tetsuzo Ueda

Tetsuzo Ueda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10529841
    Abstract: A field effect transistor having a reduced sheet resistance is provided. A channel layer, a first spacer layer, a second spacer layer, a first electronic barrier layer, and a second electronic barrier layer are sequentially grown on the main surface of a substrate. A gate recess is created, and then an ion implanted section is formed. A third electronic barrier layer and a p-type layer are formed by a metalorganic chemical vapor deposition (MOCVD) method. The p-type layer except a portion at the gate recess is removed. B ions are implanted in the regrown third electronic barrier layer to reform the ion implanted section. A source electrode and a drain electrode are formed on the third electronic barrier layer. Then a gate electrode is formed on the p-type layer.
    Type: Grant
    Filed: July 25, 2016
    Date of Patent: January 7, 2020
    Assignee: Panasonic Corporation
    Inventors: Ryo Kajitani, Kenichiro Tanaka, Masahiro Ishida, Tetsuzo Ueda
  • Patent number: 10453776
    Abstract: A semiconductor device includes a semiconductor module including a semiconductor element, a passive element, a cooling member, a first conductive member and a second conductive member. The cooling member is disposed between the semiconductor module and the passive element. And a first conductive member and a second conductive member electrically connect the semiconductor module and the passive element. Furthermore, two or more aspects of at least one of the first conductive member and the second conductive member face the cooling member.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: October 22, 2019
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Ryosuke Usui, Tetsuzo Ueda
  • Patent number: 10355143
    Abstract: A nitride semiconductor device includes: a substrate having a first major surface and a second major surface; a first nitride semiconductor layer of an n-type which is disposed on the first major surface and has a protrusion; a second nitride semiconductor layer of a p-type disposed on the protrusion; a first anode electrode disposed above the first nitride semiconductor layer and the second nitride semiconductor layer; and a cathode electrode disposed under the second major surface, and a lateral surface of the protrusion is inclined by a first angle with respect to the first major surface.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: July 16, 2019
    Assignee: PANASONIC CORPORATION
    Inventors: Ryo Kajitani, Daisuke Shibata, Kenichiro Tanaka, Satoshi Tamura, Masahiro Ishida, Tetsuzo Ueda
  • Patent number: 10249748
    Abstract: A nitride semiconductor device includes: a substrate of a first conductivity type having a first surface and a second surface on a side of the substrate opposite the first surface; a first nitride semiconductor layer of the first conductivity type which is disposed on the first surface of the substrate and includes an acceptor impurity; a second nitride semiconductor layer of a second conductivity type disposed on the first nitride semiconductor layer, the second conductivity type being opposite to the first conductivity type; a first electrode disposed on the second surface of the substrate; a second electrode disposed on the first nitride semiconductor layer; and a gate electrode disposed on the second nitride semiconductor layer.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: April 2, 2019
    Assignee: Panasonic Corporation
    Inventors: Ryo Kajitani, Daisuke Shibata, Kenichiro Tanaka, Masahiro Ishida, Tetsuzo Ueda
  • Patent number: 10128363
    Abstract: Provided is a field-effect transistor (FET) that achieves compatibility between a higher current density and lower contact resistance and exhibits excellent properties, and a method for producing the FET. The FET includes: a channel layer above a substrate; an InAlN layer above the channel layer; an InxAlyGa1-(x+y)N layer on the InAlN layer, where 0<x<1, 0<y<1, and x+y<1; and a source electrode and a drain electrode formed on the InxAlyGa1-(x+y)N layer.
    Type: Grant
    Filed: June 11, 2015
    Date of Patent: November 13, 2018
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Satoshi Nakazawa, Tetsuzo Ueda
  • Publication number: 20180097123
    Abstract: A nitride semiconductor device includes: a substrate having a first major surface and a second major surface; a first nitride semiconductor layer of an n-type which is disposed on the first major surface and has a protrusion; a second nitride semiconductor layer of a p-type disposed on the protrusion; a first anode electrode disposed above the first nitride semiconductor layer and the second nitride semiconductor layer; and a cathode electrode disposed under the second major surface, and a lateral surface of the protrusion is inclined by a first angle with respect to the first major surface.
    Type: Application
    Filed: November 17, 2017
    Publication date: April 5, 2018
    Inventors: Ryo Kajitani, Daisuke Shibata, Kenichiro Tanaka, Satoshi Tamura, Masahiro Ishida, Tetsuzo Ueda
  • Publication number: 20170365698
    Abstract: A nitride semiconductor device includes: a substrate of a first conductivity type having a first surface and a second surface on a side of the substrate opposite the first surface; a first nitride semiconductor layer of the first conductivity type which is disposed on the first surface of the substrate and includes an acceptor impurity; a second nitride semiconductor layer of a second conductivity type disposed on the first nitride semiconductor layer, the second conductivity type being opposite to the first conductivity type; a first electrode disposed on the second surface of the substrate; a second electrode disposed on the first nitride semiconductor layer; and a gate electrode disposed on the second nitride semiconductor layer.
    Type: Application
    Filed: September 5, 2017
    Publication date: December 21, 2017
    Inventors: Ryo KAJITANI, Daisuke SHIBATA, Kenichiro TANAKA, Masahiro ISHIDA, Tetsuzo UEDA
  • Patent number: 9842905
    Abstract: A semiconductor device includes: a channel layer made of GaN; a barrier layer formed on the channel layer, the bather layer being made of AlGaN and having a larger band gap than the channel layer; a p-type GaN layer selectively formed on the barrier layer; a gate electrode made of ITO on the p-type GaN layer; and a source electrode and a drain electrode on regions of the barrier layer laterally outward of the gate electrode. The width of the gate electrode in the gate length direction is smaller than or equal to the width of the p-type GaN layer in the gate length direction, and the difference between the width of the gate electrode in the gate length direction and the width of the p-type GaN layer in the gate length direction is less than or equal to 0.2 ?m.
    Type: Grant
    Filed: December 16, 2013
    Date of Patent: December 12, 2017
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Yusuke Kinoshita, Satoshi Tamura, Yoshiharu Anda, Tetsuzo Ueda
  • Patent number: 9837496
    Abstract: A semiconductor device includes: a channel layer which is made of InpAlqGa1-p-qN (0?p+q?1, 0?p, and 0?q); a barrier layer which is formed on the channel layer and is made of InrAlsGa1-r-sN (0?r+s?1, 0?r) having a bandgap larger than that of the channel layer; a diffusion suppression layer which is selectively formed on the barrier layer and is made of IntAluGa1-t-uN (0?t+u?1, 0?t, and s>u); a p-type conductive layer which is formed on the diffusion suppression layer and is made of InxAlyGa1-x-yN (0?x+y?1, 0?x, and 0?y) having p-type conductivity; and a gate electrode which is formed on the p-type conductive layer.
    Type: Grant
    Filed: November 2, 2015
    Date of Patent: December 5, 2017
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Yusuke Kinoshita, Satoshi Tamura, Tetsuzo Ueda
  • Patent number: 9666664
    Abstract: An object is to achieve an increase in gain by reducing a current collapse, and reducing Cgd and Rg. A semiconductor device according to the present invention includes a substrate; a first semiconductor layer disposed on the substrate and made of a Group III nitride semiconductor; a second semiconductor layer disposed on the first semiconductor layer and made of a Group III nitride semiconductor; a gate electrode, a source electrode, and a drain electrode disposed on the second semiconductor layer; a first field plate electrode disposed on the second semiconductor layer; and a second field plate electrode disposed on the first field plate electrode, in which the first field plate electrode and the second field plate electrode are disposed between the gate electrode and the drain electrode.
    Type: Grant
    Filed: March 19, 2015
    Date of Patent: May 30, 2017
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Ryo Kajitani, Tetsuzo Ueda, Yoshiharu Anda, Naohiro Tsurumi, Satoshi Nakazawa
  • Patent number: 9595606
    Abstract: A field-effect transistor includes a codoped layer made of AlxGa1-xN (0?x?1) and formed on a p-type Si substrate, a GaN layer formed on the codoped layer, and an AlGaN layer formed on the GaN layer. The codoped layer contains C and Si as impurity elements. The impurity concentration of C in the codoped layer is equal to or higher than 5×1017/cm3. The impurity concentration of Si in the codoped layer is lower than the impurity concentration of C. The impurity concentration of C in the GaN layer is equal to or lower than 1×1017/cm3. The thickness of the GaN layer is equal to or greater than 0.75 ?m.
    Type: Grant
    Filed: July 2, 2015
    Date of Patent: March 14, 2017
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Kenichiro Tanaka, Shinichi Kohda, Masahiro Ishida, Tetsuzo Ueda
  • Publication number: 20160336437
    Abstract: A field effect transistor having a reduced sheet resistance is provided. A channel layer, a first spacer layer, a second spacer layer, a first electronic barrier layer, and a second electronic barrier layer are sequentially grown on the main surface of a substrate. A gate recess is created, and then an ion implanted section is formed. A third electronic barrier layer and a p-type layer are formed by a metalorganic chemical vapor deposition (MOCVD) method. The p-type layer except a portion at the gate recess is removed. B ions are implanted in the regrown third electronic barrier layer to reform the ion implanted section. A source electrode and a drain electrode are formed on the third electronic barrier layer. Then a gate electrode is formed on the p-type layer.
    Type: Application
    Filed: July 25, 2016
    Publication date: November 17, 2016
    Inventors: RYO KAJITANI, KENICHIRO TANAKA, MASAHIRO ISHIDA, TETSUZO UEDA
  • Patent number: 9484342
    Abstract: A semiconductor apparatus includes a substrate; a nitride semiconductor layer formed on the substrate; a transistor formed on the nitride semiconductor layer, and including a source electrode, a gate electrode, and a drain electrode disposed in this order; and a diode formed on the nitride semiconductor layer, and including an anode electrode and a cathode electrode disposed in this order. The semiconductor apparatus has a transistor/diode pair in which the source electrode, the gate electrode, the drain electrode, the anode electrode, and the cathode electrode are sequentially disposed in this order, and the drain electrode of the transistor and the anode electrode of the diode are connected by a drain/anode common electrode wiring and serve as a common electrode.
    Type: Grant
    Filed: November 11, 2015
    Date of Patent: November 1, 2016
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Hiroyuki Handa, Hidekazu Umeda, Satoshi Tamura, Tetsuzo Ueda
  • Publication number: 20160307822
    Abstract: A semiconductor device includes a semiconductor module including a semiconductor element, a passive element, a cooling member, a first conductive member and a second conductive member. The cooling member is disposed between the semiconductor module and the passive element. And a first conductive member and a second conductive member electrically connect the semiconductor module and the passive element. Furthermore, two or more aspects of at least one of the first conductive member and the second conductive member face the cooling member.
    Type: Application
    Filed: June 29, 2016
    Publication date: October 20, 2016
    Inventors: RYOSUKE USUI, TETSUZO UEDA
  • Patent number: 9406668
    Abstract: A power semiconductor element includes: a main transistor including a first gate electrode, a first drain electrode, and a first source electrode; a sensor transistor including a second gate electrode, a second drain electrode, and a second source electrode; and a gate switch transistor including a third gate electrode, and a third drain electrode, a third source electrode. The first gate electrode, the second gate electrode, and the third drain electrode are connected, the first drain electrode and the second drain electrode are connected, the first source electrode and the second source electrode are connected via a sensor resistor, the first source electrode and the third source electrode are connected, the second source electrode and the third gate electrode are connected via a switch resistor, and the main transistor, the sensor transistor, and the gate switch transistor are formed with a nitride semiconductor.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: August 2, 2016
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Shuichi Nagai, Daisuke Ueda, Tatsuo Morita, Tetsuzo Ueda
  • Patent number: 9401403
    Abstract: A nitride semiconductor structure of the present disclosure comprises a semiconductor substrate, and a layer formed over the semiconductor substrate and comprising plural nitride semiconductor layers. The semiconductor substrate has, from a side thereof near the layer comprising the plural nitride semiconductor layers, a surface region and an internal region in this order. The surface region has a resistivity of 0.1 ?cm or more, and the internal region has a resistivity of 1000 ?cm or more.
    Type: Grant
    Filed: March 2, 2015
    Date of Patent: July 26, 2016
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Hidekazu Umeda, Masahiro Ishida, Tetsuzo Ueda, Daisuke Ueda
  • Publication number: 20160064376
    Abstract: A semiconductor apparatus includes a substrate; a nitride semiconductor layer formed on the substrate; a transistor formed on the nitride semiconductor layer, and including a source electrode, a gate electrode, and a drain electrode disposed in this order; and a diode formed on the nitride semiconductor layer, and including an anode electrode and a cathode electrode disposed in this order. The semiconductor apparatus has a transistor/diode pair in which the source electrode, the gate electrode, the drain electrode, the anode electrode, and the cathode electrode are sequentially disposed in this order, and the drain electrode of the transistor and the anode electrode of the diode are connected by a drain/anode common electrode wiring and serve as a common electrode.
    Type: Application
    Filed: November 11, 2015
    Publication date: March 3, 2016
    Inventors: HIROYUKI HANDA, HIDEKAZU UMEDA, SATOSHI TAMURA, TETSUZO UEDA
  • Publication number: 20160056245
    Abstract: A semiconductor device includes: a channel layer which is made of InpAlqGa1-p-qN (0?p+q?1, 0?p, and 0?q); a barrier layer which is formed on the channel layer and is made of InrAlsGa1-r-sN (0?r+s?1, 0?r) having a bandgap larger than that of the channel layer; a diffusion suppression layer which is selectively formed on the barrier layer and is made of IntAluGa1-t-uN (0?t+u?1, 0?t, and s>u); a p-type conductive layer which is formed on the diffusion suppression layer and is made of InxAlyGa1-x-yN (0?x+y?1, 0?y) having p-type conductivity; and a gate electrode which is formed on the p-type conductive layer.
    Type: Application
    Filed: November 2, 2015
    Publication date: February 25, 2016
    Inventors: YUSUKE KINOSHITA, SATOSHI TAMURA, TETSUZO UEDA
  • Publication number: 20160056150
    Abstract: A power semiconductor element includes: a main transistor including a first gate electrode, a first drain electrode, and a first source electrode; a sensor transistor including a second gate electrode, a second drain electrode, and a second source electrode; and a gate switch transistor including a third gate electrode, and a third drain electrode, a third source electrode. The first gate electrode, the second gate electrode, and the third drain electrode are connected, the first drain electrode and the second drain electrode are connected, the first source electrode and the second source electrode are connected via a sensor resistor, the first source electrode and the third source electrode are connected, the second source electrode and the third gate electrode are connected via a switch resistor, and the main transistor, the sensor transistor, and the gate switch transistor are formed with a nitride semiconductor.
    Type: Application
    Filed: February 25, 2014
    Publication date: February 25, 2016
    Inventors: Shuichi NAGAI, Daisuke UEDA, Tatsuo MORITA, Tetsuzo UEDA
  • Patent number: 9231059
    Abstract: A semiconductor device includes a substrate; a carrier traveling layer formed on the substrate, made of first group III nitride semiconductor, and containing carriers traveling in a direction along a principal surface of the substrate; a barrier layer formed on the carrier traveling layer and made of second group III nitride semiconductor having a wider band gap than the first group III nitride semiconductor; and an electrode formed on the barrier layer. The device further includes a cap layer formed on the barrier layer at a side of the electrode, and made of third group III nitride semiconductor containing a mixture of single crystals and polycrystals.
    Type: Grant
    Filed: December 11, 2013
    Date of Patent: January 5, 2016
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Noboru Negoro, Hidekazu Umeda, Nanako Hirashita, Tetsuzo Ueda