Abstract: This invention relates to certain 5-arylpyrimidine compounds or a pharmaceutically acceptable salt thereof, and compositions containing said compounds or a pharmaceutically acceptable salt thereof, wherein said compounds are anti-cancer agents useful for the treatment of cancer in mammals. This invention further relates to a method of treating or inhibiting the growth of cancerous tumor cells and associated diseases in a mammal and further provides a method for the treatment or prevention of cancerous tumors that express multiple drug resistance (MDR) or are resistant because of MDR, in a mammal in need thereof which method comprises administering to said mammal an effective amount of said compounds or a pharmaceutically acceptable salt thereof.

Abstract: This invention relates to certain 6-[(substituted)phenyl]triazolopyrimidine compounds or pharmaceutically acceptable salts thereof, and compositions containing said compounds or pharmaceutically acceptable salts thereof, wherein said compounds are anti-cancer agents useful for the treatment of cancer in mammals. This invention further relates to a method of treating or inhibiting the growth of cancerous tumor cells and associated diseases in a mammal and further provides a method for the treatment or prevention of cancerous tumors that express multiple drug resistance (MDR) or are resistant because of MDR, in a mammal in need thereof which method comprises administering to said mammal an effective amount of said compounds or pharmaceutically acceptable salts thereof.

Abstract: A method and system for increasing flexibility, I/O accessibility, and reliability of multicore, multiprocessor architecture, a first input/output (I/O) controller and a second I/O controller are coupled by an I/O controller link card. The first I/O controller is coupled to at least one multicore processor. A plurality of primary I/O slots and a plurality of secondary I/O slots are respectively coupled to the first I/O controller and the second I/O controller. The I/O controller link card is removably insertable in adjacent slots spanning one of the primary I/O slots and one of the secondary I/O slots, thereby providing a flexible link to electrically couple the first I/O controller and the second I/O controller.

Abstract: Current sensing is performed in a non-volatile storage device for a non-volatile storage element. A voltage is applied to a selected word line of the first non-volatile storage element, and source and p-well voltages are applied to a source and a p-well, respectively, associated with the non-volatile storage element. The source and p-well voltages are regulated at respective positive DC levels to avoid a ground bounce, or voltage fluctuation, which would occur if the source voltage at least was regulated at a ground voltage. A programming condition of the non-volatile storage element is determined by sensing a current in a NAND string of the non-volatile storage element. The sensing can occur quickly since there is no delay in waiting for the ground bounce to settle.

Abstract: Bit line-to-bit line noise is discharged in a NAND string prior to sensing a programming condition of a selected non-volatile storage element in the NAND string. A source voltage is applied which boosts the voltage in conductive NAND strings. The voltage boost results in capacitive coupling of noise to neighboring NAND strings. A current pull down device is used to discharge each NAND string prior to performing sensing. After each NAND string is coupled to a discharge path for a predetermined amount of time, bit lines of the NAND string are coupled to voltage sense components for sensing the programming condition of the selected non-volatile storage elements based on a potential of the bit lines. The selected non-volatile storage elements may have a negative threshold voltage. Further, a word line associated with the selected non-volatile storage elements may be set at ground.

Abstract: A NAND string in which bit line-to-bit line noise is discharged prior to sensing a programming condition of a selected non-volatile storage element in the NAND string. A source voltage is applied which boosts the voltage in conductive NAND strings. The voltage boost results in capacitive coupling of noise to neighboring NAND strings. A current pull down device is used to discharge each NAND string prior to performing sensing. After each NAND string is coupled to a discharge path for a predetermined amount of time, bit lines of the NAND string are coupled to voltage sense components for sensing the programming condition of the selected non-volatile storage elements based on a potential of the bit lines. The selected non-volatile storage elements may have a negative threshold voltage. Further, a word line associated with the selected non-volatile storage elements may be set at ground.

Abstract: Bit line-to-bit line noise is discharged in a NAND string prior to sensing a programming condition of a selected non-volatile storage element in the NAND string. A source voltage is applied which boosts the voltage in conductive NAND strings. The voltage boost results in capacitive coupling of noise to neighboring NAND strings. A current pull down device is used to discharge each NAND string prior to performing sensing. After each NAND string is coupled to a discharge path for a predetermined amount of time, bit lines of the NAND string are coupled to voltage sense components for sensing the programming condition of the selected non-volatile storage elements based on a potential of the bit lines. The selected non-volatile storage elements may have a negative threshold voltage. Further, a word line associated with the selected non-volatile storage elements may be set at ground.

Abstract: Current sensing is performed in a non-volatile storage device for a selected non-volatile storage element with a negative threshold voltage. A control gate read voltage is applied to a selected word line of a non-volatile storage element, and source and p-well voltages are applied to a source and a p-well, respectively, associated with the non-volatile storage element. The source and p-well voltages exceed the control gate read voltage so that a positive control gate read voltage can be used. There is no need for a negative charge pump to apply a negative word line voltage even for sensing a negative threshold voltage. A programming condition of the non-volatile storage element is determined by sensing a voltage drop which is tied to a fixed current which flows in a NAND string of the non-volatile storage element.

Abstract: A source line bias error caused by a voltage drop in a source line of a non-volatile memory device during a read or verify operation is addressed. In one approach, a body bias is applied to a substrate of the non-volatile memory device by coupling the substrate to a source voltage or a voltage which is a function of the source voltage. In another approach, a control gate voltage and/or drain voltage, e.g., bit line voltage, are compensated by referencing them to a voltage which is based on the source voltage instead of to ground. Various combinations of these approaches can be used as well. During other operations, such as programming, erase-verify and sensing of negative threshold voltages, the source line bias error is not present, so there is no need for a bias or compensation. A forward body bias can also be compensated.

Abstract: A source line bias error caused by a voltage drop in a source line of a non-volatile memory device during a read or verify operation is addressed. In one approach, a body bias is applied to a substrate of the non-volatile memory device by coupling the substrate to a source voltage or a voltage which is a function of the source voltage. In another approach, a control gate voltage and/or drain voltage, e.g., bit line voltage, are compensated by referencing them to a voltage which is based on the source voltage instead of to ground. Various combinations of these approaches can be used as well. During other operations, such as programming, erase-verify and sensing of negative threshold voltages, the source line bias error is not present, so there is no need for a bias or compensation. A forward body bias can also be compensated.

Abstract: For use in a storage area network (SAN), a virtualization layer including at least one virtual engine having a respective local cache and a secondary cache layer, wherein the secondary cache layer includes the local caches coupled together, the local caches individually including a first cache layer, and at least one of a data transfer command and data corresponding to the transfer command are multicast to the secondary cache layer through an interconnection bus, the interconnection bus coupling the at least one virtual engine and at least one physical storage device.

Abstract: A method and apparatus of calibrating filtering of receive and transmit signals is disclosed. The method of calibrating filtering of a received signal includes injecting an LO signal. The injected LO signal is filtered by a tunable filter. The filtered signal is frequency down-converted with an equivalent LO signal. The frequency down-converted signal is sampled while tuning the filtering. A desired filter tuning is determined based upon the samples and a frequency of the LO signal. The method of calibrating filtering of a transmit signal includes injecting an LO signal to a transmitter. The LO signal is filtered by a tunable filter. The filtered signal is frequency down-converted with an equivalent LO signal. The frequency down-converted signal is sampled while tuning the filter. A desired filter tuning is determined based upon the samples and a frequency of the LO signal.

Abstract: Current sensing is performed in a non-volatile storage device for a non-volatile storage element. A voltage is applied to a selected word line of the first non-volatile storage element, and source and p-well voltages are applied to a source and a p-well, respectively, associated with the non-volatile storage element. The source and p-well voltages are regulated at respective positive DC levels to avoid a ground bounce, or voltage fluctuation, which would occur if the source voltage at least was regulated at a ground voltage. A programming condition of the non-volatile storage element is determined by sensing a current in a NAND string of the non-volatile storage element. The sensing can occur quickly since there is no delay in waiting for the ground bounce to settle.

Abstract: A non-volatile storage system in which temperature compensation of a bit line voltage is provided during a sense operation of a non-volatile storage element. A gate voltage of a transistor which couples a bit line associated with the non-volatile storage element to a sense module is temperature-compensated so that it is higher when temperature is higher to compensate for variations with temperature of the bit line voltage. The bit line voltage, in turn, varies due to variations in temperature of a threshold voltage of the non-volatile storage element. The sense module determines a programming condition of the non-volatile storage element, which may be provided in a NAND string, by sensing a voltage. The sense operation may be a read operation, verify operation, or erase-verify operation, for instance. Further, the threshold voltage of the non-volatile storage element may be positive or negative. In another aspect, a source voltage is temperature compensated.

Abstract: Current sensing is performed in a non-volatile storage device for a selected non-volatile storage element with a negative threshold voltage. A control gate read voltage is applied to a selected word line of a non-volatile storage element, and source and p-well voltages are applied to a source and a p-well, respectively, associated with the non-volatile storage element. The source and p-well voltages exceed the control gate read voltage so that a positive control gate read voltage can be used. There is no need for a negative charge pump to apply a negative word line voltage even for sensing a negative threshold voltage. A programming condition of the non-volatile storage element is determined by sensing a voltage drop which is tied to a fixed current which flows in a NAND string of the non-volatile storage element.

Abstract: Temperature-compensation is provided during a sense operation of a non-volatile storage element. A gate voltage of a transistor which couples a bit line associated with the non-volatile storage element to a sense module is temperature-compensated so that it is higher when temperature is higher to compensate for variations with temperature of the bit line voltage. The bit line voltage, in turn, varies due to variations in temperature of a threshold voltage of the non-volatile storage element. The sense module determines a programming condition of the non-volatile storage element, which may be provided in a NAND string, by sensing a voltage. The sense operation may be a read operation, verify operation, or erase-verify operation, for instance. Further, the threshold voltage of the non-volatile storage element may be positive or negative. In another aspect, a source voltage is temperature compensated.

Abstract: A non-volatile storage device in which current sensing is performed for a non-volatile storage element. A voltage is applied to a selected word line of the first non-volatile storage element, and source and p-well voltages are applied to a source and a p-well, respectively, associated with the non-volatile storage element. The source and p-well voltages are regulated at respective positive DC levels to avoid a ground bounce, or voltage fluctuation, which would occur if the source voltage at least was regulated at a ground voltage. A programming condition of the non-volatile storage element is determined by sensing a current in a NAND string of the non-volatile storage element. The sensing can occur quickly since there is no delay in waiting for the ground bounce to settle.

Abstract: A pull down circuit pulls a bit line voltage to a regulated source voltage in a non-volatile storage device during a sense operation such as a verify operation which occurs during programming. The storage device may include NAND strings which have associated bit lines and sense components, and a common source line. When a selected storage element of a NAND string has been programmed to its intended state, the bit line is locked out during subsequent verify operations which occur for other NAND strings which are not yet locked out. The pull down device is coupled to each bit line and to the common source line, whose voltage is regulated at a positive DC level, to prevent coupling of system power bus (VSS) noise from the locked out bit lines to the not yet locked out bit lines.

Abstract: A non-volatile storage device in which current sensing is performed for a non-volatile storage element with a negative threshold voltage. A control gate read voltage is applied to a selected word line of a non-volatile storage element, and source and p-well voltages are applied to a source and a p-well, respectively, associated with the non-volatile storage element. The source and p-well voltages exceed the control gate read voltage so that a positive control gate read voltage can be used. There is no need for a negative charge pump to apply a negative word line voltage even for sensing a negative threshold voltage. A programming condition of the non-volatile storage element is determined by sensing a voltage drop which is tied to a fixed current which flows in a NAND string of the non-volatile storage element.

Abstract: The present invention provides a flexible storage system through the use of portable, removable canisters holding multiple storage subsystems.