Abstract: Methods and apparatuses for determining clock failure for a multi-agent system employing a link-based interconnection scheme using a forwarded clock. For one embodiment of the invention, the cessation of the forwarded clock initiates a clock failure determination process. For one embodiment of the invention, upon a determination of clock failure, an alternate clock lane is implemented using a pre-designated data lane.

Abstract: A technique for promoting determinism among bus agents within a point-to-point (PtP) network. More particularly, embodiments of the invention relate to techniques to compensate for link latency, data skew, and clock shift within a PtP network of common system interface (CSI) bus agents.

Abstract: In some embodiments, a chip comprises control circuitry to provide inband signals, inband output ports, and transmitters to transmit the inband signals to the inband output ports. The control circuitry selectively includes loopback initiating commands in the inband signals. Other embodiments are described and claimed.

Abstract: Disclosed are embodiments of a method, apparatus and system for a low power state for a point-to-point link. During the low power state, the signal on both conductors of a differential transmit pair are driven to electrical idle. Analog activity detectors are enabled during the low power state and are disabled during normal power state. Exit from the low power state does not require a physical layer re-initialization sequence. Other embodiments are also described and claimed.

Abstract: A method for effecting an in-band reset of the physical layers of two agents interconnected through a link-based interconnection scheme. In accordance with one embodiment of the invention, a first of the two agents ceases its forwarded clock to initiate the in-band reset. Upon realization of the cessation, a second agent ceases its forwarded clock and proceeds to a reset state. The first agent then proceeds to a reset state. Subsequently, after waiting a specified period of time, both agents proceed with a re-initialization of the physical layer. In accordance with one embodiment of the invention, the re-initialization of the physical layer is effected without impacting other layers of the interconnection hierarchy.

Abstract: A method and apparatus for retraining skew compensation in an interface is presented. In one embodiment, a retraining interval is determined, and counters in the transmitting agent and receiving agent count up until the retraining interval is reached. A tracking unit used to select one of several interpolated clocks may then be powered up, and a special retraining phit may be sent across the interface. During the retraining process, the transfer of flits into and out of the flow-control mechanism may be inhibited. When the retraining process is finished, the tracking unit may be powered down.

Abstract: In some embodiments, a chip comprising transmitters, local receivers, and control circuitry to determine whether the transmitters are coupled to remote receivers through interconnects. If certain conditions are met the control circuitry causes the transmitters to transmit a compliance test pattern on the interconnects. The conditions include that the control circuitry determines that the remote receivers are coupled to the transmitters and the local receivers have not received signals within a particular time. Other embodiments are described and claimed.

Abstract: A software self test engine is executed from a cache of a processor. The software self test engine is executed using an execution engine of the processor to perform a physical layer self test. The physical layer self test is performed by transmitting a test vector from the execution engine under control of the self test engine to an input/output (“I/O”) unit of the processor along a datapath coupling the execution engine to the I/O unit. The test vector is transmitted along a loop back path including the I/O unit and the datapath to test a hardware device along the loop back path.

Abstract: In some embodiments, a chip includes first and second nodes, a variable voltage source, a transmitter, change detection circuitry, and control circuitry. The transmitter includes a driver coupled to the first and second nodes, and first and second resistive structures coupled between the first and second nodes, respectively, and the variable voltage source. The change detection circuitry detects changes in voltages of the first and second nodes following a change in voltage of the variable voltage source. The control circuitry determines whether the changes in voltages of the first and second nodes are consistent with the transmitter being coupled through interconnects to a remote receiver. Other embodiments are described and claimed.

Abstract: In some embodiments, a chip includes transmitters to provide transmit signals to chip interfaces and voltage control circuitry to control voltages of the transmit signals. The chip further includes receivers to receive external signals from another chip. The chip also includes evaluation circuitry to determine whether the transmit signals were usable by the other chip based on an evaluation of at least one of the received external signals and to provide a usability indicating signal to the voltage control circuitry indicative of whether the transmit signals were usable by the other chip. Other embodiments are described and claimed.

Abstract: In some embodiments, a chip includes first and second nodes, a variable voltage source, a transmitter, change detection circuitry, and control circuitry. The transmitter includes a driver coupled to the first and second nodes, and first and second resistive structures coupled between the first and second nodes, respectively, and the variable voltage source. The change detection circuitry detects changes in voltages of the first and second nodes following a change in voltage of the variable voltage source. The control circuitry determines whether the changes in voltages of the first and second nodes are consistent with the transmitter being coupled through interconnects to a remote receiver. Other embodiments are described and claimed.

Abstract: According to one embodiment, a built-in self test (IBIST) architecture/methodology is disclosed. The IBIST provides for testing the functionality of an interconnect (such as a bus) between a transmitter and a receiver component. The IBIST architecture includes a pattern generator and a pattern checker. The pattern checker operates to compare a received plurality of bits (for the pattern generator) with a previously stored plurality of bits.

Abstract: In some embodiments, a chip comprises control circuitry to provide inband signals, inband output ports, and transmitters to transmit the inband signals to the inband output ports. The control circuitry selectively includes loopback initiating commands in the inband signals. Other embodiments are described and claimed.

Abstract: In some embodiments, a chip includes first and second nodes, a variable voltage source, and transmitter and control circuitry. The transmitter includes a driver coupled to the first and second nodes, and first and second resistive structures coupled between the first and second nodes, respectively, and the variable voltage source. The control circuitry selects an impedance level for the first and second resistive structures, and detect coupling of a remote receiver to the transmitter through interconnects and detect decoupling of the remote receiver from the transmitter. Other embodiments are described and claimed.

Abstract: In some embodiments, a chip includes first and second nodes, a variable voltage source, a transmitter, change detection circuitry, and control circuitry. The transmitter includes a driver coupled to the first and second nodes, and first and second resistive structures coupled between the first and second nodes, respectively, and the variable voltage source. The change detection circuitry detects changes in voltages of the first and second nodes following a change in voltage of the variable voltage source. The control circuitry determines whether the changes in voltages of the first and second nodes are consistent with the transmitter being coupled through interconnects to a remote receiver. Other embodiments are described and claimed.

Abstract: In some embodiments, a chip comprising transmitters, local receivers, and control circuitry to determine whether the transmitters are coupled to remote receivers through interconnects. If certain conditions are met the control circuitry causes the transmitters to transmit a compliance test pattern on the interconnects. The conditions include that the control circuitry determines that the remote receivers are coupled to the transmitters and the local receivers have not received signals within a particular time. Other embodiments are described and claimed.