Abstract: An MRAM module configuration in which, in order to increase the packing density, memory cell zones containing memory arrays and peripheral circuits are nested in one another. In this manner, an increased packing density of the memory cell is achieved which results in lowered production costs and a smaller chip space for a more compact configuration.

Abstract: An integrated memory has a multiplexer and a differential sense amplifier with a differential input. The differential sense amplifier is connected to three bit lines by the multiplexer. The multiplexer electrically connects the differential input of the sense amplifier to any two of the three bit lines connected to it respectively, in accordance with its activation.

Abstract: A digital circuit configuration includes a memory matrix having M rows and N columns and P<M additional rows and Q<N additional columns, and an addressing device whose address connection contacts are sufficient precisely for addressing the M rows and N columns. To address the additional rows and columns as well, particularly, for test purposes, only a single control bit connection contact is provided with a changeover device responding to control bits from the control bit connection contact and from dedicated address connection contacts to associate applied address bits either with addressing of the M rows and N columns or the additional rows and columns. The numbers P and Q are chosen such that the addressing of P elements requires at least two bits fewer than the addressing of M elements, and such that the addressing of Q elements requires at least two bits fewer than the addressing of N elements.

Abstract: An integrated memory contains two normal read amplifiers and two first redundant read amplifiers. It also contains bit lines which are combined into at least two individually addressable normal columns, at least one of which from each normal column is connected to one of the normal read amplifiers. It also has first redundant bit lines which are combined into one individually addressable redundant column, at least one of which is connected to one of the redundant read amplifiers. The first redundant read amplifier and its redundant columns are provided for replacing the two normal read amplifiers and one of the normal columns.

Abstract: A semiconductor memory device has a particularly space-saving configuration of the memory areas and, in particular, of the selection devices assigned to the memory areas. During operation, each selection device can be assigned in a controllable manner to a plurality of memory areas such that selectively each of the selection devices can carry out an addressing and selection in one of the assigned memory areas.

Abstract: The memory has identically constructed memory cells and reference cells. An item of reference information is written into the reference cells by uncoupling the reference cells from the read amplifiers via first switching elements, and by electrically connecting the part of the bit lines that is connected to the reference cells via second switching elements to a potential line carrying the reference information.

Abstract: A current driver configuration for MRAMs includes word-line drivers and bit-line drivers at respective first ends of word lines and bit lines. The word line drivers and the bit line drivers each include a series circuit formed by an n-channel field-effect transistor and a current source. Further series circuits are provided at the respective second ends of the word lines and the bit lines. Each of the further series circuits includes a second n-channel field-effect transistor and a voltage source.

Abstract: A decoder element is provided with an output, whereby an output signal with one of three different possible potentials is produced. The output signal may have a value of either a first potential, a second potential, and a third potential, where the second potential lies between the first potential and the third potential. The output signal is produced according to voltage values of input signals at terminal connections of the decoder element.

Abstract: A magneto-resistive random access memory (MRAM) configuration is described in which line driver circuits are respectively assigned via connecting nodes to two memory cell arrays, with the result that the area for the driver circuits can practically be halved. Therefore a space-saving architecture and a more efficient MRAM configuration is obtained.

Abstract: The memory cell configuration has a large number of memory cells provided in a semiconductor substrate and having bit-line trenches which extend in parallel in the longitudinal direction in the main face of the semiconductor substrate, at the bottoms of which in each case a first conductive region is provided, at the peaks of which in each case a second conductive region of the same conduction type as the first conductive region is provided, and in the walls of which in each case an intermediately located channel region is 0 provided; and having word lines which extend in the transverse direction along the main face of the semiconductor substrate, through specific bit-line trenches, to activate transistors provided there. An additional dopant is introduced into the trench walls of the bit-line trenches which are located between the word lines, in order to increase the corresponding transistor turn-on voltage there to suppress leakage currents.

Abstract: An integrated memory has two first switching elements, which respectively connect a bit line of a first bit line pair to a bit line of a second bit line pair. In addition, the integrated memory has two second switching elements, which respectively connect one of the reference cells of one bit line pair to that bit line of the other bit line pair which is not connected via the corresponding first switching element to the bit line assigned to this reference cell. Information is written back to the reference cells via the sense amplifiers. A method of operating the integrated memory is also provided.

Abstract: In a semiconductor memory configuration, a refresh operation is always started by a refresh logic circuit when a comparison circuit determines that there is a specific minimum difference when comparing a characteristic variable of at least one reference memory cell with a reference value (VREF).

Abstract: The integrated memory has m>1 bit lines that are connected to an input of a read-write amplifier via a switching element. Only one switching element is conductively connected for each read or write access. The memory is provided with a switching unit that influences read or write access occurring by way of the read-write amplifier and bit lines. The circuit unit is provided with an activation input. A column-end decoder has a first decoder stage and m second decoder stages. The outputs of the second decoder stages are connected to a control input for each of the switching elements. The output of the first decoder stage is connected to the activation input of the switching unit.

Abstract: A CMOS voltage divider having a first chain containing series-connected MOS transistors of a first conductivity type is described. Each of the MOS transistors have identical geometrical dimensions and, at the same time, each have identical gate-source voltages. The MOS transistors operate in the linear range of their characteristic curve and between opposite ends of the first chain an input voltage to be divided is present and at whose source terminals the voltage fractions can in each case be picked off. Provision is made of a second chain containing series-connected MOS transistors, complementary to the first MOS transistors. The second chain has the same number of transistors as the first MOS transistors and with the same geometrical dimension in each case. The MOS transistors of the first chain are connected to the MOS transistors of the second chain in such a way that each MOS transistor chain generates the gate-source bias voltage for the respective other MOS transistor chain.

Abstract: Method for operating, a helium leak indicator (1) consisting of a helium detector (4) with evacuation devices comprising at least a high-vacuum pump (6), a backing pump (9) and a valve (16) whose level of flow conductance can be adjusted and serves to modulate the through-flow of test gas to be analyzed; in order to influence the sensitivity in a simple manner, the method provides that the modulation properties be changeable in such a manner that the effective pumping capacity at the inlet of the leak indicator is changed by the adjustment of the modulation properties.

Abstract: An MRAM module configuration in which, in order to increase the packing density, memory cell zones containing memory arrays and peripheral circuits are nested in one another. In this manner, an increased packing density of the memory cell is achieved which results in lowered production costs and a smaller chip space for a more compact configuration.

Abstract: An integrated memory has two first switching elements, which respectively connect a bit line of a first bit line pair to a bit line of a second bit line pair. In addition, the integrated memory has two second switching elements, which respectively connect one of the reference cells of one bit line pair to that bit line of the other bit line pair which is not connected via the corresponding first switching element to the bit line assigned to this reference cell. Information is written back to the reference cells via the sense amplifiers. A method of operating the integrated memory is also provided.

Abstract: The decoder element is used for producing an output signal having three different potentials at an output. The second potential is situated between the first potential and the third potential. The decoder element makes it possible to produce any one of the three potentials at its output based upon the potentials on its connections.

Abstract: An integrated memory has a multiplexer and a differential sense amplifier with a differential input. The differential sense amplifier is connected to three bit lines by the multiplexer. The multiplexer electrically connects the differential input of the sense amplifier to any two of the three bit lines connected to it respectively, in accordance with its activation.

Abstract: The memory has identically constructed memory cells and reference cells. An item of reference information is written into the reference cells by uncoupling the reference cells from the read amplifiers via first switching elements, and by electrically connecting the part of the bit lines that is connected to the reference cells via second switching elements to a potential line carrying the reference information.