Abstract: An assembly includes a chip including an integrated circuit, a casing including an integrated circuit including plural active elements and having an upper portion formed on a side of the chip and lower portion formed on another side of the chip, plural through-wafer vias (TWVs) for electrically connecting the integrated circuit of the chip and the integrated circuit of the casing, and a card connected to the casing for electrically connecting the casing to a system board.

Abstract: A computer-implemented method, system, and article of manufacture for optimizing heat transfer in a 3-D chip-stack. The method includes the steps of: receiving a heat-removal effectiveness parameter for a plurality of channel-region areas in the chip-stack, receiving at least one of a flow value and temperature value for at least two of the channel-region areas, comparing the received values for different channel-region areas, and adjusting a flow rate of a liquid flowing to at least one of the two channel-region areas based on the heat-removal effectiveness parameter of the channel-region area receiving the adjustment and the results of the comparison step, where at least one step is carried out using a computer device.

Abstract: A computer program product or hardware description language (“HDL”) design structure in a computer-aided design system for generating a functional design model of an integrated circuitry structure including generating a functional representation of at least first and second regions of the integrated circuitry structure, generating a functional representation of an optical layer comprising optical waveguides, and generating a functional representation of a heat-conductive material for transferring heat from at least the second region through the optical layer to a heat sink.

Abstract: An integrated circuitry structure includes at least first and second regions. An optical layer includes optical waveguides. A heat-conductive material transfers heat from at least the second region through the optical layer to a heat sink.

Abstract: A method in a computer-aided design system for generating a functional design model of an integrated circuitry structure including generating a functional representation of at least first and second regions of the integrated circuitry structure, generating a functional representation of an optical layer comprising optical waveguides, and generating a functional representation of a heat-conductive material for transferring heat from at least the second region through the optical layer to a heat sink.

Abstract: An integrated device includes at least one heat generating component which generates heat when operated, at least one temperature-sensitive component, and one or more hollow insulation regions arranged between the at least one heat generating component and the at least one temperature-sensitive component. The hollow insulation region may be provided as a vacuum gap.

Abstract: An integrated circuit coupling device includes an integrated circuit package; and an optical data transmission medium connected to the integrated circuit package, and comprising a movable coolant, adapted to remove heat from the integrated circuit package, in operation.

Abstract: An integrated device includes at least one heat generating component which generates heat when operated, at least one temperature-sensitive component, and one or more hollow insulation regions arranged between the at least one heat generating component and the at least one temperature-sensitive component. The hollow insulation region may be provided as a vacuum gap.

Abstract: An integrated circuit coupling device includes an integrated circuit package with N integrated circuit layers (L1-LN) arranged as a 3D stack; and a data transmission medium with n data transmission layers (l1-ln), wherein n?1 and N?2, and wherein the N integrated circuit layers are electrically connectable to the n data transmission layers.

Abstract: A method in a computer-aided design system for generating a functional design model of an integrated circuitry structure including generating a functional representation of at least first and second regions of the integrated circuitry structure, generating a functional representation of an optical layer comprising optical waveguides, and generating a functional representation of a heat-conductive material for transferring heat from at least the second region through the optical layer to a heat sink.

Abstract: An assembly includes a chip including an integrated circuit, a casing including an integrated circuit and having an upper portion formed on a side of the chip and lower portion formed on another side of the chip, plural through-wafer vias (TWVs) for electrically connecting the integrated circuit of the chip and the integrated circuit of the casing, and a card connected to the casing for electrically connecting the casing to a system board. The card includes an upper card connected to the upper portion of the casing, and a lower card connected to the lower portion of the casing. The upper card includes one of a photosensor, light emitting element, radio frequency (RF) antenna, and radio frequency emitter. The lower card includes an area array input/output.

Abstract: An assembly includes a chip including an integrated circuit, a casing including an integrated circuit including plural active elements and having an upper portion formed on a side of the chip and lower portion formed on another side of the chip, plural through-wafer vias (TWVs) for electrically connecting the integrated circuit of the chip and the integrated circuit of the casing, and a card connected to the casing for electrically connecting the casing to a system board.

Abstract: An assembly includes a chip including an integrated circuit, a casing including an integrated circuit and having an upper portion formed on a side of the chip and lower portion formed on another side of the chip, plural through-wafer vias (TWVs) for electrically connecting the integrated circuit of the chip and the integrated circuit of the casing, and a card connected to the casing for electrically connecting the casing to a system board.

Abstract: A computer-implemented method, system, and article of manufacture for optimizing heat transfer in a 3-D chip-stack. The method includes the steps of: receiving a heat-removal effectiveness parameter for a plurality of channel-region areas in the chip-stack, receiving at least one of a flow value and temperature value for at least two of the channel-region areas, comparing the received values for different channel-region areas, and adjusting a flow rate of a liquid flowing to at least one of the two channel-region areas based on the heat-removal effectiveness parameter of the channel-region area receiving the adjustment and the results of the comparison step, where at least one step is carried out using a computer device.

Abstract: A method for manufacturing a filling in a gap region between a first surface and a second surface includes applying a suspension comprising a carrier fluid and filler particles in the gap region between the first and the second surface; and withholding filler particles by a barrier element in the gap region to form a path of attached filler particles between the first surface and the second surface.

Abstract: An assembly includes a chip including an integrated circuit, a casing including an integrated circuit and having an upper portion formed on a side of the chip and lower portion formed on another side of the chip, plural through-wafer vias (TWVs) for electrically connecting the integrated circuit of the chip and the integrated circuit of the casing, and a card connected to the casing for electrically connecting the casing to a system board.

Abstract: A mechanism is provided for optimizing semiconductor packing in a three-dimensional (3D) very-large-scale integration (VLSI) device. The 3D VLSI device comprises a processor layer coupled, via a first set of coupling devices, to at least one signaling and input/output (I/O) layer. The 3D VLSI device further comprises a power delivery layer coupled, via a second set of coupling devices, to the processor layer. In the 3D VLSI device the power delivery layer is dedicated to only delivering power and does not provide data communication signals to the elements of the three-dimensional VLSI device, and the at least one signaling and input/output (I/O) layer is dedicated to only transmitting the data communication signals to and receiving the data communications signals from the processor layer and does not provide power to the elements of the processor layer.

Abstract: A mechanism is provided for a thermal power plane that delivers power and constitutes minimal thermal resistance. The mechanism comprises a processor layer coupled, via a first set of coupling devices, to a signaling and input/output (I/O) layer and a power delivery layer coupled, via a second set of coupling devices, to the processor layer. In the mechanism, the power delivery layer is dedicated to only delivering power and does not provide data communication signals to the elements of the mechanism. In the mechanism, the power delivery layer comprises a plurality of conductors, a plurality of insulating materials, one or more ground planes, and a plurality of through laminate vias. In the mechanism, the signaling and input/output (I/O) layer is dedicated to only transmitting the data communication signals to and receiving the data communications signals from the processor layer and does not provide power to the elements of the processor layer.

Abstract: A mechanism is provided for integrated power delivery and distribution via a heat sink. The mechanism comprises a processor layer coupled to a signaling and input/output (I/O) layer via a first set of coupling devices and a heat sink coupled to the processor layer via a second set of coupling devices. In the mechanism, the heat sink comprises a plurality of grooves on one face, where each groove provides either a path for power or a path for ground to be delivered to the processor layer. In the mechanism, the heat sink is dedicated to only delivering power and does not provide data communication signals to the elements of the mechanism and the signaling and I/O layer is dedicated to only transmitting the data communication signals to and receiving the data communications signals from the processor layer and does not provide power to the elements of the processor layer.

Abstract: An electronic device having an electrode with enhanced injection properties comprising a first electrode and a first layer of cross-linked molecular charge transfer material on the first electrode. The cross-linked molecular charge transfer material may be an acceptor, which may consist of at least one of: TNF, TN9(CN)2F, TeNF, TCNB, DCNQ, and TCAQ. The cross-linked molecular charge transfer material may also be a donor, which may consist of at least one of: Terpy, Ru(terpy)2 TTN, and crystal violet.