Abstract: A solid-state memory including an array of magnetic storage cells and a set of conductors. The process steps that pattern the conductors also patterns the magnetic layers in the magnetic storage cells thereby avoiding the need to employ precise alignment between pattern masks.

Abstract: A conductor structure for a magnetic memory is disclosed. The conductor structure includes one or more conductors that have a width that is less than a dimension of a memory cell in a direction the conductor crosses the memory cell. A thickness of the conductor is preselected to reduce a cross-sectional area of the conductor and increase a current density within the conductor. A magnetic field sufficient to rotate an alterable orientation of magnetization in a data layer of the memory cell can be generated by a reduced magnitude of a current flowing in the conductor due to the increased current density. Alternatively, the magnitude of the current can be reduced by increasing a thickness of the conductor to increase its area and reduce its resistance to the flow of electrons and partially cladding the conductor to reduce a total magnetic path around the conductor thereby increasing the magnetic field.

Abstract: A magnetic memory device includes first and second ferromagnetic layers. Each ferromagnetic layer has a magnetization that can be oriented in either of two directions. The first ferromagnetic layer has a higher coercivity than the second ferromagnetic layer. The magnetic memory device further includes a structure for forming a closed flux path with the second ferromagnetic layer.

Abstract: A one-time programmable (“OTP”) memory includes one or more memory arrays stacked on top of each other. The OTP memory array is a cross-point array where unit memory cells are formed at the cross-points. The unit memory cell may include a fuse and an anti-fuse in series with each other or may include a vertically oriented fuse. Programming the memory may include the steps of selecting unit memory cells, applying a writing voltage such that critical voltage drop across the selected cells occur. This causes the anti-fuse of the cell to break down to a low resistance. The low resistance of the anti-fuse causes a high current pulse to be delivered to the fuse, which in turn melts the fuse to an open state. Reading the memory may include the steps of selecting unit memory cells for reading, applying a reading voltage to the selected memory cells and measuring whether current is present or not. Equipotential sensing may be used to read the memory.

Abstract: A one-time programmable memory cell includes a fuse and an anti-fuse in series. The memory cell has two states, an initial state and a written (programmed) state. In the initial state, a resistance of the cell is finite, typically dominated by the relatively high resistance of the anti-fuse. In the written state, the resistance is infinite because the breakdown of the fuse resulting in an open circuit. The cell may be programmed by applying a critical voltage across the cell generating a critical current to cause the fuse to become open. When critical voltage is applied, this generally causes the anti-fuse to break down, which in turn causes a pulse of high current to be applied to the fuse. The states are detected by applying a read voltage across the memory cell. If the memory has not been programmed, then a measurable amount flows. Otherwise, no current flows.

Abstract: A memory cell includes a conductor clad with ferromagnetic material; first and second spacer layers on opposite sides of the clad conductor; a first data layer on the first spacer layer; and a second data layer on the second spacer layer.

Abstract: A write line structure for a magnetic memory cell includes a write conductor having a front surface facing the memory cell, a back surface and two sides surfaces. A cladding layer is disposed adjacent a portion of the front surface of the write conductor, with the cladding layer terminating at spaced first and second poles adjacent the front surface of the write conductor. A data storage layer is operatively positioned adjacent the cladding layer. The distance between the poles is less than the width of the write conductor. The width of the data storage layer may be greater than or less than the distance between the poles.

Abstract: A one-time programmable unit memory cell includes a vertically oriented fuse and an diode in series. Within the vertically oriented fuse, the current flow is substantially vertical, i.e. perpendicular to the plane of the substrate. Also, the vertically oriented fuse is placed between top and bottom conductors. This vertical placement of the elements helps to increase density of memory devices built using these unit cells. Also, vertically oriented fuses consume very little lateral area, which helps the density even further. The unit memory cell has two states, an initial state and a written (programmed) state. In the initial state, a resistance of the cell is finite because the vertically oriented fuse is left intact. In the written state, the resistance is infinite because the fuse is blown open. The cell may be programmed by applying a critical voltage across the cell enough to cause the fuse to become open. The states are detected by applying a read voltage across the memory cell.

Abstract: A one-time programmable memory cell includes a fuse and an anti-fuse in series. The memory cell has two states, an initial state and a written (programmed) state. In the initial state, a resistance of the cell is finite, typically dominated by the relatively high resistance of the anti-fuse. In the written state, the resistance is infinite because the breakdown of the fuse resulting in an open circuit. The cell may be programmed by applying a critical voltage across the cell generating a critical current to cause the fuse to become open. When critical voltage is applied, this generally causes the anti-fuse to break down, which in turn causes a pulse of high current to be applied to the fuse. The states are detected by applying a read voltage across the memory cell. If the memory has not been programmed, then a measurable amount flows. Otherwise, no current flows.

Abstract: Vertically oriented nano-circuits including fuses and resistors allow for significant densities to be achieved. The vertically oriented nano-circuits can be fabricated using standard known processes such as Damascene, wet etching, reactive etching, etc. Thus little additional capital expenditure is required other than to acquire present state-of-the-art equipment. Devices using these vertically oriented nano-circuits are also inexpensive to manufacture.

Abstract: A one-time programmable unit memory cell includes a vertically oriented fuse and an diode in series. Within the vertically oriented fuse, the current flow is substantially vertical, i.e. perpendicular to the plane of the substrate. Also, the vertically oriented fuse is placed between top and bottom conductors. This vertical placement of the elements helps to increase density of memory devices built using these unit cells. Also, vertically oriented fuses consume very little lateral area, which helps the density even further. The unit memory cell has two states, an initial state and a written (programmed) state. In the initial state, a resistance of the cell is finite because the vertically oriented fuse is left intact. In the written state, the resistance is infinite because the fuse is blown open. The cell may be programmed by applying a critical voltage across the cell enough to cause the fuse to become open. The states are detected by applying a read voltage across the memory cell.

Abstract: A one-time programmable (“OTP”) memory includes one or more memory arrays stacked on top of each other. The OTP memory array is a cross-point array where unit memory cells are formed at the cross-points. The unit memory cell may include a fuse and an anti-fuse in series with each other or may include a vertically oriented fuse. Programming the memory may include the steps of selecting unit memory cells, applying a writing voltage such that critical voltage drop across the selected cells occur. This causes the anti-fuse of the cell to break down to a low resistance. The low resistance of the anti-fuse causes a high current pulse to be delivered to the fuse, which in turn melts the fuse to an open state. Reading the memory may include the steps of selecting unit memory cells for reading, applying a reading voltage to the selected memory cells and measuring whether current is present or not. Equipotential sensing may be used to read the memory.

Abstract: A method for fabricating a magnetoresistive memory cell with improved roughness uniformity and reduced roughness amplitude of a selected layer of material in the magnetoresistive memory cell by smoothing at an atomic scale an interface surface of the selected layer is disclosed. The smoothing is accomplished by irradiating an interface surface of the selected layer with a collimated beam of gas cluster ions that are accelerated along a beam bath by predetermined acceleration voltage. The gas cluster ions bombard the interface surface and upon impact therewith, the gas cluster ions disintegrate in a direction that is substantially lateral to the beam path. As a result, the gas cluster ions laterally sputter the interface surface and remove one or more monolayers of material from the interface surface. Consequently, an initial surface roughness of the interface surface is reduced and homogenized (i.e. made uniform) to a final surface roughness.

Abstract: A tunnel junction having a topography and/or interface layers that enhance its magneto-resistance. The topography of the tunnel junction maximizes spin tunneling from areas of ferromagnetic crystalline grains having high polarization and minimizes the effects of defect scattering at grain boundaries. The interface layers enhance magnetic polarization properties of ferromagnetic layers near interfaces to an insulating layer in a tunnel junction.

Abstract: A random access memory (memory) includes one or more planes of memory arrays stacked on top of each other. Each plane may be manufactured separately, and each array within the plane may be enabled/disabled separately. In this manner, each memory array within the plane can be individually tested, and defective memory arrays may be sorted out, which increases the final yield and quality. A memory plane may be stacked on top of each other and on top of an active circuit plane to make a large capacity memory device. The memory may be volatile or non-volatile by using appropriate memory cells as base units. Also, the memory plane may be fabricated separately from the active circuitry. Thus the memory plane does not require a silicon substrate, and may be formed from a glass substrate for example. Further, each memory plane may be individually selected (or enabled) via plane memory select transistors. The array may be individually selected (or enable) via array select transistor.

Abstract: A method for cladding two or three sides of a top conductor for a magnetic memory device in ferromagnetic material includes forming a trench with side walls in a coating layer above the memory device. A first ferromagnetic material is deposited along the side walls of the trench. Any ferromagnetic material in a bottom of the trench can be removed. A conductor material is deposited in the trench over the memory device. A second ferromagnetic material is deposited over the conductor material in the trench to form a cladding of the ferromagnetic material around three side of the conductor.

Abstract: A memory device includes dual tunnel junction memory cells having a magnetic tunnel junction in series with a tunnel junction. The magnetic tunnel junction can be changed from a first resistance state to a second resistance state during a write operation. The magnetic tunnel junction can have a differing resistance-voltage characteristic than the tunnel junction, and the differing resistance-voltage characteristics allow the magnetic tunnel junction to be blown without blowing the tunnel junction during a write operation. The change in resistance state of the magnetic tunnel junction changes the resistance of the selected memory cell, which is detectable during a read operation.

Abstract: A data storage device includes a resistive cross point array of memory cells. Each memory cell includes a memory element and a resistive element connected in series with the memory element. The resistive elements substantially attenuate any sneak path currents flowing through shorted memory elements during read operations. The data storage device may be a Magnetic Random Access Memory (“MRAM”) device.

Abstract: A method for cladding two or three sides of a top conductor for a magnetic memory device in ferromagnetic material includes forming a trench with side walls in a coating layer above the memory device. A first ferromagnetic material is deposited along the side walls of the trench. Any ferromagnetic material in a bottom of the trench can be removed. A conductor material is deposited in the trench over the memory device. A second ferromagnetic material is deposited over the conductor material in the trench to form a cladding of the ferromagnetic material around three sides of the conductor.

Abstract: A tunnel junction having a topography and/or interface layers that enhance its magneto-resistance. The topography of the tunnel junction maximizes spin tunneling from areas of ferromagnetic crystalline grains having high polarization and minimizes the effects of defect scattering at grain boundaries. The interface layers enhance magnetic polarization properties of ferromagnetic layers near interfaces to an insulating layer in a tunnel junction.