Abstract: A semiconductor device includes: a semiconductor substrate having opposing first and second main surfaces; a plurality of transistor cells each including a source region, a drift zone, a body region separating the source region from the drift zone, a field plate trench extending into the drift zone and including a field plate, and a planar gate on the first main surface and configured to control current through a channel of the body region; a drain region at the second main surface; and a diffusion barrier structure including alternating layers of Si and oxygen-doped Si and a Si capping layer on the alternating layers of Si and oxygen-doped Si. The diffusion barrier structure may be interposed between body regions of adjacent transistor cells and/or extend along the channel of each transistor cell and/or vertically extend in the semiconductor substrate between adjacent field plate trenches.

Abstract: A projector assembly with at least one light source, which is connected downstream of a gobo screen, is disclosed. The gobo screen has a gobo aperture diaphragm and a gobo lens. A projection lens is connected downstream of the gobo screen. In addition, an aperture diaphragm is connected downstream of the gobo screen. The light emitted by the light source is focused in the aperture diaphragm via the gobo lens. The image from the gobo screen is displayed in the far field via the projection lens.

Abstract: An electronic component includes a semiconductor device including a semiconductor die including a first surface, the first surface including a first metallization structure and edge regions surrounding the first metallization structure, a second surface opposing the first surface and including a second metallization structure, and side faces extending between the first surface and the second surface, wherein the edge regions of the first surface and portions of the side faces are covered by a first polymer layer, wherein the electronic component further includes a plurality of leads and a plastic housing composition, wherein the first metallization structure is coupled to a first lead and the second metallization structure is coupled to a second lead of the plurality of leads.

Abstract: A semiconductor device includes: a semiconductor substrate having opposing first and second main surfaces; a plurality of transistor cells each including a source region, a drift zone, a body region separating the source region from the drift zone, a field plate trench extending into the drift zone and including a field plate, and a planar gate on the first main surface and configured to control current through a channel of the body region; a drain region at the second main surface; and a diffusion barrier structure including alternating layers of Si and oxygen-doped Si and a Si capping layer on the alternating layers of Si and oxygen-doped Si. The diffusion barrier structure may be interposed between body regions of adjacent transistor cells and/or extend along the channel of each transistor cell and/or vertically extend in the semiconductor substrate between adjacent field plate trenches.

Abstract: Disclosed is a transistor device which includes a semiconductor body having a first surface, a source region, a drift region, a body region being arranged between the source region and the drift region, a gate electrode adjacent the body region and dielectrically insulated from the body region by a gate dielectric, and a field electrode adjacent the drift region and dielectrically insulated from the drift region by a field electrode dielectric, wherein the field electrode comprises a first layer and a second layer, wherein the first layer has a lower electrical resistance than the second layer, wherein a portion of the second layer is disposed above and directly contacts a portion of the first layer.

Abstract: The disclosure relates to a semiconductor die, including a vertical power transistor device, a pull-down transistor device, and a capacitor. The pull-down transistor device is connected between a gate electrode of the vertical power transistor device and a ground terminal and connects the gate electrode to the ground terminal in a conducting state. The capacitor is connected between one of the load terminals of the vertical power transistor device and the control terminal of the pull-down transistor device and capacitively couples the one load terminal to the control terminal.

Abstract: The disclosure relates to a semiconductor die with a transistor device, having a source region, a drain region, a body region including a channel region, a gate region, which includes a gate electrode, next to the channel region, for controlling a channel formation, a drift region between the channel region and the drain region, and a field electrode region with a field electrode formed in a field electrode trench, which extends into the drift region, wherein the channel region extends laterally and is aligned vertically with the gate region, and wherein at least a portion of the channel region is arranged vertically above the field electrode region.

Abstract: A semiconductor transistor device is described that has a source region, a body region including a vertical channel region, a drain region, a gate region laterally aside the channel region, a body contact region formed by doping, a diffusion barrier layer, and a conductive region formed of a conductive material. The body contact region electrically contacts the body region, the diffusion barrier layer being arranged in between. The doping of the body contact region is of the same conductivity type but of higher concentration than a doping of the body region. The conductive region has a contact area that forms an electrical contact to the body contact region, the contact area of the conductive region being arranged vertically above an upper end of the channel region. A method for manufacturing the semiconductor transistor device is also described.

Abstract: An electronic component includes a semiconductor device including a semiconductor die including a first surface, the first surface including a first metallization structure and edge regions surrounding the first metallization structure, a second surface opposing the first surface and including a second metallization structure, and side faces extending between the first surface and the second surface, wherein the edge regions of the first surface and portions of the side faces are covered by a first polymer layer, wherein the electronic component further includes a plurality of leads and a plastic housing composition, wherein the first metallization structure is coupled to a first lead and the second metallization structure is coupled to a second lead of the plurality of leads.

Abstract: In an embodiment, a composite semiconductor substrate includes a first polymer layer and a plurality of semiconductor dies having a first surface, a second surface opposing the first surface, side faces extending between the first surface and the second surface and a first metallization structure on the first surface. Edge regions of the first surface and at least portions of the side faces are embedded in the first polymer layer. At least one metallic region of the first metallization structure is exposed from the first polymer layer. A second metallization structure is arranged on the second surface of the plurality of semiconductor dies. A second polymer layer is arranged on edge regions of the second surface of the plurality of semiconductor dies and on the first polymer layer in regions between the side faces of neighbouring ones of the plurality of semiconductor dies.

Abstract: In an embodiment, a semiconductor package includes a first transistor device having first and second opposing surfaces, a first power electrode and a control electrode arranged on the first surface and a second power electrode arranged on the second surface. A first metallization structure arranged on the first surface includes a plurality of outer contact pads which includes a protective layer of solder, Ag or Sn. A second metallization structure is arranged on the second surface. A conductive connection extending from the first surface to the second surface electrically connects the second power electrode to an outer contact pad of the first metallization structure. A first epoxy layer arranged on side faces and on the first surface of the transistor device includes openings which define a lateral size of the plurality of outer contact pads and a package footprint.

Abstract: Disclosed is an electronic circuit. The electronic circuit includes a first transistor device and a clamping circuit. The first transistor device includes a control node and a load path between a first load node and a second load node, and the clamping circuit includes a second transistor device and a drive circuit. The second transistor device includes a control node and a load path connected in parallel with the load path of the first transistor device, and the drive circuit includes a capacitor coupled between the second load node of the first transistor device, and a first resistor coupled between the control node of the second transistor device and a further circuit node.

Abstract: A semiconductor device includes a contact opening extending through a source region and a body region of the device. An electrically insulative spacer lines sidewalls of the semiconductor substrate formed by the contact opening, and is recessed along the sidewalls such that at least part of the source region or body region is uncovered by the electrically insulative spacer. A body contact plug is in the contact opening. A first body contact region formed adjacent a bottom of the contact opening adjoins the body contact plug at the bottom of the contact opening. A second body contact region formed in the part of the source region or body region uncovered by the electrically insulative spacer adjoins the body contact plug along the part of the source region or body region uncovered by the electrically insulative spacer.

Abstract: In an embodiment, a semiconductor package includes a first transistor device having first and second opposing surfaces, a first power electrode and a control electrode arranged on the first surface and a second power electrode arranged on the second surface. A first metallization structure arranged on the first surface includes a plurality of outer contact pads which includes a protective layer of solder, Ag or Sn. A second metallization structure is arranged on the second surface. A conductive connection extending from the first surface to the second surface electrically connects the second power electrode to an outer contact pad of the first metallization structure. A first epoxy layer arranged on side faces and on the first surface of the transistor device includes openings which define a lateral size of the plurality of outer contact pads and a package footprint.

Abstract: In an embodiment, a module includes a first electronic device in a first device region and a second electronic device in a second device region. The first electronic device is operably coupled to the second electronic device to form a circuit. Side faces of the first electronic device and of the second electronic device are embedded in, and in direct contact with, a first epoxy layer.

Abstract: A semiconductor device includes a trench extending into a first main surface of a semiconductor substrate, and a gate electrode and a gate dielectric in the trench. The gate dielectric separates the gate electrode from the semiconductor substrate. A first region having a first conductivity type is formed in the semiconductor substrate at the first surface adjacent the trench. A second region having a second conductivity type is formed in the semiconductor substrate below the first region adjacent the trench. A third region having the first conductivity type is formed in the semiconductor substrate below the second region adjacent the trench. A contact opening in the semiconductor substrate extends into the second region. An electrically insulative spacer is disposed on sidewalls of the semiconductor substrate formed by the contact opening, and an electrically conductive material in the contact opening adjoins the electrically insulative spacer on the sidewalls.

Abstract: Disclosed is a transistor device which includes a semiconductor body having a first surface, a source region, a drift region, a body region being arranged between the source region and the drift region, a gate electrode adjacent the body region and dielectrically insulated from the body region by a gate dielectric, and a field electrode adjacent the drift region and dielectrically insulated from the drift region by a field electrode dielectric, wherein the field electrode comprises a first layer and a second layer, wherein the first layer has a lower electrical resistance than the second layer, wherein a portion of the second layer is disposed above and directly contacts a portion of the first layer.

Abstract: An optical system includes optical fibers, a decoupling surface, an intersecting surface and a connecting portion. The optical fibers are arranged in at least one row. Each of the optical fibers includes a coupling surface onto which light from a light source is received. Light is directed through the optical fibers along an optical main axis. Light emitted from the optical fibers is directed onto a decoupling surface. The connecting portion is planar and is disposed between the decoupling surface and the optical fibers. The intersecting surface bounds the decoupling surface and is parallel to the optical main axis. Each of the optical fibers has an intersecting face oriented parallel to the optical main axis and parallel to the intersecting surface. The intersecting surface and the intersecting faces of the optical fibers generate a sharp outer edge of a light pattern formed by light emitted from the optical system.

Abstract: In various embodiments, an optical unit for a radiation source matrix is provided. The optical unit may include a plurality of coupling surfaces, which are arranged in at least one line, and at least one decoupling surface. At least one coupling surface, which is arranged at a line end of the line formed by the coupling surfaces arranged in at least one line, is widened when viewed in the direction of the at least one line.

Abstract: Disclosed is a transistor device which includes a semiconductor body having a first surface, a source region, a drift region, a body region being arranged between the source region and the drift region, a gate electrode adjacent the body region and dielectrically insulated from the body region by a gate dielectric, and a field electrode adjacent the drift region and dielectrically insulated from the drift region by a field electrode dielectric. The field electrode includes a first layer and a second layer. The second layer includes a different conductive material as the first layer. A portion of the second layer is disposed above and directly contacts a portion of the first layer.