Patents by Inventor Thomas Hecht

Thomas Hecht has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070137844
    Abstract: In a plate heat exchanger having a heat exchanger block (1) with a number of heat exchange passages and a header (2) attached to the heat exchanger block, the header providing a flow connection between a portion of the heat exchange passages and a fluid connection (3), the header is defined by a cylinder jacket segment-shaped wall (7) and by a flat surface (12), which runs parallel to the axis of the cylinder (13) on a side (5) of the heat exchanger block. The length of the header extends over at least one portion of a side (5) of the heat exchanger block. At least one wall (7) of the header is connected to the side (5) of the heat exchanger block. The header is designed so that the axis (13) of the cylinder runs inside the header spaced at a distance (11) from the flat surface (12).
    Type: Application
    Filed: December 1, 2006
    Publication date: June 21, 2007
    Inventors: Herbert Aigner, Gabriele Engl, Thomas Hecht, Stefan Moller, Wolfgang Sussmann, Alfred Wanner
  • Publication number: 20070114014
    Abstract: A plate heat exchanger includes a heat exchanger block having a plurality of heat exchange passages. On the heat exchanger block, a header is mounted that extends over at least one part of one side of the heat exchanger block and establishes a flow connection between part of the heat exchange passages. The plate heat exchanger is provided with a fluid connection, which is formed by the header-side end of a pipeline. The fluid connection is essentially perpendicular to the side of the heat exchanger block over which the header extends. Within the pipeline directly in front of its end, there is a flow guide.
    Type: Application
    Filed: October 31, 2006
    Publication date: May 24, 2007
    Applicant: Linde Aktiengesellschaft
    Inventors: Herbert Aigner, Gabriele Engl, Thomas Hecht, Helge Mobus, Stefan Moller, Wolfgang Sussmann, Alfred Wanner
  • Publication number: 20070114244
    Abstract: Disclosed are systems and methods for dispensing flavor doses and beverages. A beverage tower may be provided that has a small footprint and that is capable of dispensing a wide variety of flavor doses and blended beverages. The beverage tower may include a flow control module that controls the flow rate of beverage additives and water through the beverage tower and a switch module that includes a plurality of switches that may be selectively opened and closed to control the flow of beverage additives and water through the beverage tower to a point of dispense. A flavor dose or blended beverage may be dispensed by the beverage tower in accordance with user input that is provided to the beverage tower via a control panel. The user input may specify a desired beverage additive, a desired cup size, and an indication of whether a flavor shot or a blended beverage is desired.
    Type: Application
    Filed: November 6, 2006
    Publication date: May 24, 2007
    Inventors: Shaun Gatipon, Douglas McDougall, Byron Eberhart, Thomas Hecht, Roland Young, Richard Martindale, Bret Baker
  • Publication number: 20070111547
    Abstract: In a method for producing a semiconductor structure a substrate is provided, a dielectric layer comprising at least one metal oxide is formed on the substrate, and a nitrided layer is formed from the dielectric layer. The nitrided layer comprises either at least one metal nitride corresponding to the metal oxide or a metal oxynitride. The nitrided layer is removed selectively with respect to the dielectric layer in a predetermined etching medium.
    Type: Application
    Filed: October 18, 2006
    Publication date: May 17, 2007
    Inventors: Thomas Hecht, Stefan Jakschik, Christian Kapteyn
  • Patent number: 7176514
    Abstract: A method for producing a dielectric layer on a substrate made of a conductive substrate material includes reducing a leakage current that flows through defects of the dielectric layer at least by a self-aligning and self-limiting electrochemical conversion of the conductive substrate material into a nonconductive substrate follow-up material in sections of the substrate that are adjacent to the defects. Also provided is a configuration including a dielectric layer with defects, a substrate made of a conductive substrate material, and reinforcement regions made of the nonconductive substrate follow-up material in sections adjacent to the defects.
    Type: Grant
    Filed: April 15, 2003
    Date of Patent: February 13, 2007
    Assignee: Infineon Technologies AG
    Inventors: Thomas Hecht, Albert Birner, Harald Seidl, Uwe Schröder, Stefan Jakschik, Martin Gutsche
  • Publication number: 20070007624
    Abstract: The present invention relates to a method of fabricating a capacitor in a semiconductor substrate. The capacitor is fabricated such that the capacitor comprises: a trench inside a substrate, the trench having a lower region and an upper region, wherein the trench's diameters in the lower region is larger than in the upper region; a first electrode; a dielectric layer on top of the first electrode; a conductive layer on top of the electric layer, the conductive layer forming a second electrode of the capacitor; and a plug forming a closed cavity inside the lower region.
    Type: Application
    Filed: July 11, 2005
    Publication date: January 11, 2007
    Inventors: Christian Kapteyn, Stephan Kudelka, Thomas Hecht
  • Patent number: 7157371
    Abstract: A dielectric barrier layer composed of a metal oxide is applied in thin layers with a thickness of less than 20 nanometers in the course of processing semiconductor devices by sequential gas phase deposition or molecular beam epitaxy in molecular individual layers on differently structured base substrates. The method allows, inter alias, effective conductive diffusion barriers to be formed from a dielectric material, an optimization of the layer thickness of the barrier layer, an increase in the temperature budget for subsequent process steps, and a reduction in the effort for removing the temporary barrier layers.
    Type: Grant
    Filed: September 2, 2003
    Date of Patent: January 2, 2007
    Assignee: Infineon Technologies AG
    Inventors: Thomas Hecht, Uwe Schroeder, Harald Seidl, Martin Gutsche, Stefan Jakschik, Stephan Kudelka, Albert Birner
  • Publication number: 20060275981
    Abstract: Memory and method for fabricating it A memory formed as an integrated circuit in a semiconductor substrate and having storage capacitors and switching transistors. The storage capacitors are formed in the semiconductor substrate in a trench and have an outer electrode layer, which is formed around the trench, a dielectric intermediate layer, which is embodied on the trench wall, and an inner electrode layer, with which the trench is essentially filled, and the switching transistors are formed in the semiconductor substrate in a surface region and have a first source/drain doping region, a second source/drain doping region and an intervening channel, which is separated from a gate electrode by an insulator layer.
    Type: Application
    Filed: May 30, 2006
    Publication date: December 7, 2006
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Alejandro Avellan, Matthias Goldbach, Thomas Hecht, Stefan Jakschik, Andreas Orth, Uwe Schroder, Michael Stadtmueller, Olaf Storbeck
  • Patent number: 7144770
    Abstract: The invention provides a method for fabricating a memory cell, a substrate (101) being provided, a trench-type depression (102) being etched into the substrate (101), a barrier layer (103) being deposited non-conformally in the trench-type depression (102), grain elements (104) being grown on the inner areas of the trench-type depression (102), a dielectric layer (202) being deposited on the surfaces of the grain elements and the inner areas of the trench-type depression, and a conduction layer being deposited on the dielectric layer, the grain elements (104) growing selectively on the inner areas (105) of the trench-type depression (102) in an electrode region (301) forming a lower region of the trench-type depression (102) and an amorphous silicon layer continuing to grow in a collar region (302) forming an upper region of the trench-type depression (102).
    Type: Grant
    Filed: November 3, 2004
    Date of Patent: December 5, 2006
    Assignee: Infineon Technologies AG
    Inventors: Albert Birner, Matthias Foerster, Thomas Hecht, Michael Stadtmueller, Andreas Orth
  • Publication number: 20060264054
    Abstract: The present invention relates to a method for etching a trench in a semiconductor substrate. More specifically, the present invention relates to a method for etching deep trenches such as those having aspect ratios of 30 and higher. According to embodiments of the invention, a method for etching a trench in a semiconductor substrate includes a first etch cycle wherein the trench is etched to a first depth. Thereafter, a protective liner is deposited on at least the upper part of the trench's sidewalls. The protective liner includes inorganic material. During at least one second etch cycle, the trench is etched to its final depth.
    Type: Application
    Filed: April 6, 2005
    Publication date: November 23, 2006
    Inventors: Martin Gutsche, Thomas Hecht, Harald Seidl, Uwe Rudolph, Barbara Lorenz, Elisabeth Weikmann
  • Patent number: 7132337
    Abstract: Charge-trapping regions are arranged beneath lower edges of the gate electrode separate from one another. Source/drain regions are formed in self-aligned manner with respect to the charge-trapping regions by means of a doping process at low energy in order to form shallow junctions laterally extending only a small distance beneath the charge-trapping regions. The self-alignment ensures a large number of program-erase cycles with high effectiveness and good data retention, because the locations of the injections of charge carriers of opposite signs are narrowly and exactly defined.
    Type: Grant
    Filed: December 20, 2004
    Date of Patent: November 7, 2006
    Assignee: Infineon Technologies AG
    Inventors: Stefan Jakschik, Matthias Goldbach, Thomas Mikolajick, Thomas Hecht
  • Publication number: 20060234463
    Abstract: An electrical component, such as a DRAM semiconductor memory or a field-effect transistor is fabricated. At least one capacitor having a dielectric (130) and at least one connection electrode (120, 140) are fabricated. To enable the capacitors fabricated to have optimum storage properties even for very small capacitor structures, the dielectric (130) or the connection electrode (120, 140) are formed in such a manner that transient polarization effects are prevented or at least reduced.
    Type: Application
    Filed: April 7, 2006
    Publication date: October 19, 2006
    Inventors: Alejandro Avellan, Thomas Hecht, Stefan Jakschik, Uwe Schroeder
  • Publication number: 20060202250
    Abstract: A storage capacitor, suitable for use in a DRAM cell, is at least partially formed above a substrate surface and includes: a storage electrode at least partially formed above the substrate surface, a dielectric layer formed adjacent the storage electrode, and a counter electrode formed adjacent the dielectric layer, the counter electrode being isolated from the storage electrode by the dielectric layer, wherein the storage electrode is formed as a body which is delimited by at least one curved surface having a center of curvature outside the body in a plane parallel to the substrate surface. According to another configuration, the storage electrode is formed as a body which is delimited by at least one set having two contiguous planes, the two planes extending perpendicularly with respect to the substrate surface, a point of intersection of normals of the two planes lying outside the body.
    Type: Application
    Filed: March 10, 2005
    Publication date: September 14, 2006
    Inventors: Thomas Hecht, Uwe Schroeder, Till Schloesser, Stefan Jakschik, Alejandro Avellan
  • Patent number: 7100280
    Abstract: The invention relates to a method for producing a plate heat exchanger from a plurality of heat exchanger blocks (1a, 1b). Each heat exchanger block (1a, 1b) has mounted on it a header (6a, 7a, 6b, 7b) which extends over at least part of one side of the heat exchanger block (1a, 1b). The heat exchanger blocks (1a, 1b) are arranged next to one another, and the headers (6a, 6b; 7a, 7b) of two adjacent heat exchanger blocks (1a, 1b) are provided on their mutually confronting sides with orifices and are connected to one another in such a way that a flow connection occurs between the two headers (6a, 6b; 7a, 7b).
    Type: Grant
    Filed: February 25, 2004
    Date of Patent: September 5, 2006
    Assignee: Linde Aktiengesellschaft
    Inventors: Stefan Moeller, Alfred Wanner, Gabriele Engl, Thomas Hecht, Wolfgang Suessmann, Herbert Aigner
  • Patent number: 7087485
    Abstract: A method for fabricating patterned ceramic layers on areas of a relief structure, wherein the layers may be arranged essentially perpendicular to a top side of a substrate. In exemplary embodiments, a patterned ceramic layer forms an oxide collar for a trench capacitor. The oxide collar is produced by a trench firstly being filled with a resist in its lower section, and an oxide layer subsequently being produced on the uncovered areas of the substrate with the aid of a low temperature ALD method. By means of anisotropic etching, only those portions of the ceramic layer which are arranged at the perpendicular walls of the trench remain. The resist filling may subsequently be removed, for example, by means of an oxygen plasma.
    Type: Grant
    Filed: January 28, 2004
    Date of Patent: August 8, 2006
    Assignee: Infineon Technologies AG
    Inventors: Harald Seidl, Martin Gutsche, Thomas Hecht
  • Publication number: 20060157493
    Abstract: A dispensing apparatus for dispensing a lid from a stack of lids each having a lid periphery includes a load platform having a main floor on which to place a stack of lids, the main floor sloping downward from an apex in a rearward direction, the load platform having a forward slope inclined downward from the apex in a forward direction. A parallelogram mechanism is mounted to move in a linear direction forward to a dispense position and rearward to a home position. A hinge is coupled to the parallelogram mechanism and has a handle with a distal end oriented upward and forward to contact an inner surface of a lid periphery of a bottommost lid of the stack of lids when the parallelogram mechanism moves forward from the home position toward the dispense position.
    Type: Application
    Filed: October 12, 2005
    Publication date: July 20, 2006
    Applicant: Redi-Lid LP
    Inventors: Steve Christoffersen, Thomas Hecht, Scott Thompson, Michael Simi
  • Publication number: 20060134871
    Abstract: Charge-trapping regions are arranged beneath lower edges of the gate electrode separate from one another. Source/drain regions are formed in self-aligned manner with respect to the charge-trapping regions by means of a doping process at low energy in order to form shallow junctions laterally extending only a small distance beneath the charge-trapping regions. The self-alignment ensures a large number of program-erase cycles with high effectiveness and good data retention, because the locations of the injections of charge carriers of opposite signs are narrowly and exactly defined.
    Type: Application
    Filed: December 20, 2004
    Publication date: June 22, 2006
    Inventors: Stefan Jakschik, Matthias Goldbach, Thomas Mikolajick, Thomas Hecht
  • Publication number: 20060127576
    Abstract: In a process chamber of a process reactor, a sequential gas phase deposition (ALD, atomic layer deposition) of two or more precursors fed in by means of process gases is controlled. The process chamber is connected to an auxiliary chamber for a change of precursor and so the precursor to be removed is rarefied in the process chamber, so that a process duration of the sequential gas phase deposition that is determined by a change of precursor is reduced.
    Type: Application
    Filed: September 24, 2003
    Publication date: June 15, 2006
    Inventors: Thomas Hecht, Jorn Lutzen
  • Patent number: 7051798
    Abstract: The invention relates to a plate heat exchanger with a heat exchanger block which has a multiplicity of heat exchange passages. The heat exchanger block has mounted on it a header which extends over at least part of one side of the heat exchanger block and makes a flow connection between part of the heat exchange passages. The header is provided with a fluid connection which is arranged essentially perpendicularly to that side of the heat exchanger block over which the header extends. (FIG.
    Type: Grant
    Filed: February 25, 2004
    Date of Patent: May 30, 2006
    Assignee: Linde Aktiengesellschaft
    Inventors: Stefan Moeller, Alfred Wanner, Gabriele Engl, Thomas Hecht, Wolfgang Suessmann, Herbert Aigner
  • Patent number: 7041568
    Abstract: A structure on a layer surface of the semiconductor wafer has at least one first area region (8, 9), which is reflective for electromagnetic radiation, and at least one second, essentially nonreflecting area region (10, 11, 12). A light-transmissive insulation layer (13) and a light-sensitive layer are produced on said layer surface. The electromagnetic radiation is directed onto the light-sensitive layer with an angle ? of incidence and the structure of the layer surface is imaged with a lateral offset into the light-sensitive layer.
    Type: Grant
    Filed: July 18, 2002
    Date of Patent: May 9, 2006
    Assignee: Infineon Technologies AG
    Inventors: Matthias Goldbach, Thomas Hecht, Jörn Lützen, Bernhard Sell