Abstract: The present invention relates to compounds that are MALT1 inhibitors. The compounds have the structural formula I defined herein. The present invention also relates to processes for the preparation of these compounds, to pharmaceutical compositions comprising them, and to their use in the treatment of diseases or disorders associated with MALT1.

Abstract: An approach for correcting at least one byte error in a binary sequence is proposed, the binary sequence comprising a plurality of bytes and being a code word of an error code in the error-free case. The approach comprises the steps of: (i) determining at least one byte error position signal which specifies whether or not a byte of the binary sequence is erroneous, (ii) determining at least one byte error correction value, based on which an erroneous byte position identified by means of the byte error position signal is correctable, the at least one byte error correction value being determined by virtue of a first value and a second value being determined for each of at least two byte positions based on a coefficient of the locator polynomial, and (iii) correcting the at least one byte error based on the at least one byte error correction value.

Abstract: A thermally broken sill leveling device securing a door or window frame member to a substructure, including: an adjuster plate having a female threaded through hole therein and configured to be secured to the frame member; an adjustment screw for threadedly engaging the female threaded hole of the adjuster plate, the adjustment screw having a through hole therein; and a locking screw for securing the adjuster plate to the substructure, the locking screw passing through the through hole of the adjustment screw and being screwed to the substructure, wherein a spacing between the frame member and the substructure is adjusted by rotatably adjusting the adjustment screw so that a distal end thereof abuts against the substructure. This adjusts the space between the frame member and the substructure.

Abstract: One embodiment describes a memory readout circuit. The memory readout circuit includes a readout node having a capacitance that is discharged by the memory cell to read out a memory cell by means of a cell current, a level detector that is configured to provide a digital output signal and to switch over the output signal when the potential of the readout node (due to the discharge of the readout node) crosses a switching threshold (depending on the selection of the level and the polarity downward or upward, that is to say the switching threshold is overshot or undershot), and a control circuit that is configured to set the switching threshold and/or the switching speed of the level detector depending on the cell current.

Abstract: The determination of a code word is proposed, wherein (i) a bit group of n memory cells is read and n states are determined therefrom, the n states being determined in a time domain for each of at least two k-out-of-n codes, the at least two k-out-of-n codes having different k, (ii) the fact of whether a code word is present is determined for each of the at least two codes on the basis of the states, and (iii) when at least one code word is present, the code word of the k-out-of-n code having the largest k is used.

Abstract: A solution is proposed for error processing, wherein n byte error positions of n byte errors are predefined (where n is a positive integer), wherein this involves determining whether there is a further byte error position on the basis of the n byte error positions and on the basis of n+1 error syndrome components of a first error code.

Abstract: In a method for accessing memory cells, a first read operation is performed on a first memory cell to read a first data value from the first memory cell. During the first read operation, a first variable current source provides a first assessment current having a first current level to a first bitline coupled to the first memory cell. A second read operation is performed on the first memory cell to read a second data value from the first memory cell. During the second read operation, the first variable current source manipulates the first current level to provide a second current level to the first bitline. A difference between the first current level and the second current level is based on whether the first data value that was read during the first read operation was a first data state or a second data state.

Abstract: Solutions are proposed related to error detection wherein (i) each byte of a second byte sequence is determined as a function of at least one byte of a first byte sequence, (ii) a byte of the second byte sequence is impermissible if it is not equal to an assigned byte of the first byte sequence and if no error of a predefined error set corrupts this byte to the assigned byte of the first byte sequence, and (iii) at least one error is detected if the second byte sequence is impermissible, the second byte sequence being impermissible if at least one byte of the second byte sequence is impermissible.

Abstract: An approach to correcting errors in a string of symbols is proposed, in which the string of symbols is transformed by a transformation ? into a first group of symbols and into a second group of symbols, and in which the group of symbols that has fewer erroneous symbols than the other group is corrected using a first error code.

Abstract: A method for storing data bits in memory cells, in which the data bits have at least one byte-filling bit, where at least one predefined functionality for a subset of the data bits is coded in the at least one byte-filling bit, and in which the data bits are stored in the memory cells. A method for reading data bits from memory cells, in which the data bits have at least one byte-filling bit, where at least one predefined functionality for a subset of the data bits is coded in the at least one byte-filling bit, and in which the data bits are read from the memory cells based on the coded predefined functionality. Corresponding apparatuses and memories are also disclosed.

Abstract: A method for storing data bits in memory cells, in which the data bits have at least one byte-filling bit, where at least one predefined functionality for a subset of the data bits is coded in the at least one byte-filling bit, and in which the data bits are stored in the memory cells. A method for reading data bits from memory cells, in which the data bits have at least one byte-filling bit, where at least one predefined functionality for a subset of the data bits is coded in the at least one byte-filling bit, and in which the data bits are read from the memory cells based on the coded predefined functionality. Corresponding apparatuses and memories are also disclosed.

Abstract: A method for determining a resultant data word when accessing memory cells includes reading a set of memory cells, and determining first and second data words therefrom. Each memory cell is assigned a component of the first and second data words. The first and second data words for the respective memory cell assume a first value if a first comparison with a first reference value and a second comparison with a second reference value show that the two reference values are greater and assume a second value if the first comparison with the first reference value and the second comparison with the second reference value show that the two reference values are smaller. The first and second data words assume at least one third value if neither condition is satisfied. The resultant data word is determined based on the first or second data words. A corresponding device is also proposed.

Abstract: An optical system for a motor vehicle headlight, wherein the system includes at least two optical elements, including a light coupling area, a light decoupling area, a lateral surface which delimits the optical element and has an optically effective aperture edge for forming a bright/dark boundary in a far-field light distribution producible with the optical system. The system includes at least two anterior optics, wherein an anterior optic is associated with each optical element. The first anterior optic and first optical element are configured to produce a first far-field light distribution, wherein the second anterior optic and second optical element are configured to produce a second far-field light distribution, which lies below the bright/dark boundary of the first far-field light distribution.

Abstract: The present invention relates to compounds that are IL-17A modulators. The compounds have the structural Formula I defined herein. The present invention also relates to processes for the preparation of these compounds, to pharmaceutical compositions comprising them, and to their use in the treatment of diseases or disorders associated with modulation of IL-17A activity.

Abstract: A solution is proposed for error processing, wherein n byte error positions of n byte errors are predefined (where n is a positive integer), wherein this involves determining whether there is a further byte error position on the basis of the n byte error positions and on the basis of n + 1 error syndrome components of a first error code.

Abstract: A memory device is provided. The memory device comprises at least one non-volatile memory cell, a write circuit configured to write to the at least one memory cell, and a read circuit configured to read from the at least one memory cell, wherein the memory device is configured to be operable in a test operating mode, in which at least one test path can be tested, and wherein the test path comprises at least a portion of the write circuit and at least a portion of the read circuit, and bypasses the at least one memory cell.

Abstract: Processing of a bit sequence is proposed, wherein (i) a first partial error syndrome s1 of an error syndrome and a second partial error syndrome s2 of the error syndrome are determined for the bit sequence, (ii) a first comparison value is determined on the basis of a bit position and the first partial error syndrome, (iii) a second comparison value is determined on the basis of the bit position and the second partial error syndrome, and (iv) the bit position is corrected should a comparison of the first comparison value with the second comparison value assume a specified value and otherwise the bit position is not corrected.

Abstract: A centering device for centering a sliding door or window, including a rail; a moving member configured to be movable along the rail; and a plurality of centering rollers fixed to one of the rail and the moving member and spaced along a length thereof corresponding to a direction of movement of the door or window along the rail, the centering rollers abutting against an other of the rail and the moving member to laterally center the moving member with respect to the rail. The centering device can be implemented in a sill, header and jamb.

Abstract: The present invention relates to compounds that are IL-17A modulators. The compounds have the structural Formula I defined herein. The present invention also relates to processes for the preparation of these compounds, to pharmaceutical compositions comprising them, and to their use in the treatment of diseases or disorders associated with modulation of IL-17A activity.

Abstract: An optical system for a motor vehicle headlight, wherein the system includes at least two optical elements, including a light coupling area, a light decoupling area, a lateral surface which delimits the optical element and which has an optically effective aperture edge for forming a bright/dark boundary in a far-field light distribution producible with the optical system. The optical system includes at least two anterior optics, wherein an anterior optic is associated with each optical element, wherein a first anterior optic is configured to direct light beams along a first coupling direction onto the light coupling area of the optical element associated with it.