Abstract: The determination of a code word is proposed, wherein (i) a bit group of n memory cells is read and n states are determined therefrom, the n states being determined in a time domain for each of at least two k-out-of-n codes, the at least two k-out-of-n codes having different k, (ii) the fact of whether a code word is present is determined for each of the at least two codes on the basis of the states, and (iii) when at least one code word is present, the code word of the k-out-of-n code having the largest k is used.

Abstract: A method for storing data bits in memory cells, in which the data bits have at least one byte-filling bit, where at least one predefined functionality for a subset of the data bits is coded in the at least one byte-filling bit, and in which the data bits are stored in the memory cells. A method for reading data bits from memory cells, in which the data bits have at least one byte-filling bit, where at least one predefined functionality for a subset of the data bits is coded in the at least one byte-filling bit, and in which the data bits are read from the memory cells based on the coded predefined functionality. Corresponding apparatuses and memories are also disclosed.

Abstract: A solution for correcting errors is proposed, wherein a bit group of n memory cells is read and n states are determined therefrom, wherein the n states are determined in a time domain for a k1-out-of-n code and for a k2-out-of-n code, where k1 is less than k2. Furthermore, for a read n-bit word, which is a non-code word instead of a code word of the k2-out-of-n code, the previously read n-bit code word of the k1-out-of-n code is used to determine possible erroneous bits in the read non-code word. Possible code words of the k2-out-of-n code are determined for the non-code word based on the possible erroneous bits, and error correction is carried out using an external error code based on the possible code words.

Abstract: Solutions are proposed related to error detection wherein (i) each byte of a second byte sequence is determined as a function of at least one byte of a first byte sequence, (ii) the second byte series is permissible if (a) it equals the corresponding byte of the first byte sequence or (b) an error being a member of a predetermined error set could cause the byte of the second byte sequence to become the byte of the first byte sequence, and otherwise (c) the byte of the second byte sequence is impermissible, and (iii) at least one error is detected if the second byte sequence is impermissible.

Abstract: The approaches proposed here relate to error processing by means of at least two error processing branches. Each of the error processing branches is configured (i) to process a data word, wherein the data words of the error processing branches differ in at least one bit, and (ii) to provide a processed data word to a decision unit. The decision unit is configured to select one of the processed data words or to perform a predetermined action if an uncorrectable error has been detected.

Abstract: A conveyor belt scales for transporting goods includes: a feed belt; a weighing belt; and a removal belt. The weighing belt is supported on a load cell that detects a weight of the goods transported by the weighing belt. The conveyor belt scales further has a metal detector, which includes a transmitter coil and a receiver coil. The transmitter coil and the receiver coil are each a planar coil.

Abstract: Solutions are proposed related to error detection wherein (i) each byte of a second byte sequence is determined as a function of at least one byte of a first byte sequence, (ii) a byte of the second byte sequence is impermissible if it is not equal to an assigned byte of the first byte sequence and if no error of a predefined error set corrupts this byte to the assigned byte of the first byte sequence, and (iii) at least one error is detected if the second byte sequence is impermissible, the second byte sequence being impermissible if at least one byte of the second byte sequence is impermissible.

Abstract: An approach to correcting errors in a string of symbols is proposed, in which the string of symbols is transformed by a transformation ? into a first group of symbols and into a second group of symbols, and in which the group of symbols that has fewer erroneous symbols than the other group is corrected using a first error code.

Abstract: Example embodiments provide a sliding system with improved mechanisms. According to embodiments, the sliding system may include a drive mechanism, a frame, a supporting device, and a connecting device. The drive mechanism is configurable to move a sliding panel along at least one track. The frame may house at least a portion of the drive mechanism. The supporting device may be detachably connected to the frame. The connecting device detachably connected the drive mechanism to the sliding panel.

Abstract: A memory device is provided. The memory device comprises at least one non-volatile memory cell, a write circuit configured to write to the at least one memory cell, and a read circuit configured to read from the at least one memory cell, wherein the memory device is configured to be operable in a test operating mode, in which at least one test path can be tested, and wherein the test path comprises at least a portion of the write circuit and at least a portion of the read circuit, and bypasses the at least one memory cell.

Abstract: An approach corrects at least one byte error in a binary sequence, the binary sequence comprising multiple bytes and being a codeword of an error code if there is no error. The approach comprises: (i) determining at least one byte error position signal indicating whether or not a byte of the binary sequence is erroneous, (ii) determining at least one byte error correction value on the basis of which an erroneous byte position identified by using the byte error position signal is able to be corrected, (iii) wherein the at least one byte error correction value is determined by determining a first value, a second value and a third value for each of at least three byte positions according to a coefficient of the locator polynomial, and (iv) correcting the at least one byte error on the basis of the at least one byte error correction value.

Abstract: An approach for correcting at least one byte error in a binary sequence is proposed, the binary sequence comprising a plurality of bytes and being a code word of an error code in the error-free case. The approach comprises the steps of: (i) determining at least one byte error position signal which specifies whether or not a byte of the binary sequence is erroneous, (ii) determining at least one byte error correction value, based on which an erroneous byte position identified by means of the byte error position signal is correctable, the at least one byte error correction value being determined by virtue of a first value and a second value being determined for each of at least two byte positions based on a coefficient of the locator polynomial, and (iii) correcting the at least one byte error based on the at least one byte error correction value.

Abstract: A thermally broken sill leveling device securing a door or window frame member to a substructure, including: an adjuster plate having a female threaded through hole therein and configured to be secured to the frame member; an adjustment screw for threadedly engaging the female threaded hole of the adjuster plate, the adjustment screw having a through hole therein; and a locking screw for securing the adjuster plate to the substructure, the locking screw passing through the through hole of the adjustment screw and being screwed to the substructure, wherein a spacing between the frame member and the substructure is adjusted by rotatably adjusting the adjustment screw so that a distal end thereof abuts against the substructure. This adjusts the space between the frame member and the substructure.

Abstract: One embodiment describes a memory readout circuit. The memory readout circuit includes a readout node having a capacitance that is discharged by the memory cell to read out a memory cell by means of a cell current, a level detector that is configured to provide a digital output signal and to switch over the output signal when the potential of the readout node (due to the discharge of the readout node) crosses a switching threshold (depending on the selection of the level and the polarity downward or upward, that is to say the switching threshold is overshot or undershot), and a control circuit that is configured to set the switching threshold and/or the switching speed of the level detector depending on the cell current.

Abstract: The determination of a code word is proposed, wherein (i) a bit group of n memory cells is read and n states are determined therefrom, the n states being determined in a time domain for each of at least two k-out-of-n codes, the at least two k-out-of-n codes having different k, (ii) the fact of whether a code word is present is determined for each of the at least two codes on the basis of the states, and (iii) when at least one code word is present, the code word of the k-out-of-n code having the largest k is used.

Abstract: A solution is proposed for error processing, wherein n byte error positions of n byte errors are predefined (where n is a positive integer), wherein this involves determining whether there is a further byte error position on the basis of the n byte error positions and on the basis of n+1 error syndrome components of a first error code.

Abstract: In a method for accessing memory cells, a first read operation is performed on a first memory cell to read a first data value from the first memory cell. During the first read operation, a first variable current source provides a first assessment current having a first current level to a first bitline coupled to the first memory cell. A second read operation is performed on the first memory cell to read a second data value from the first memory cell. During the second read operation, the first variable current source manipulates the first current level to provide a second current level to the first bitline. A difference between the first current level and the second current level is based on whether the first data value that was read during the first read operation was a first data state or a second data state.

Abstract: Solutions are proposed related to error detection wherein (i) each byte of a second byte sequence is determined as a function of at least one byte of a first byte sequence, (ii) a byte of the second byte sequence is impermissible if it is not equal to an assigned byte of the first byte sequence and if no error of a predefined error set corrupts this byte to the assigned byte of the first byte sequence, and (iii) at least one error is detected if the second byte sequence is impermissible, the second byte sequence being impermissible if at least one byte of the second byte sequence is impermissible.

Abstract: An approach to correcting errors in a string of symbols is proposed, in which the string of symbols is transformed by a transformation ? into a first group of symbols and into a second group of symbols, and in which the group of symbols that has fewer erroneous symbols than the other group is corrected using a first error code.

Abstract: A method for storing data bits in memory cells, in which the data bits have at least one byte-filling bit, where at least one predefined functionality for a subset of the data bits is coded in the at least one byte-filling bit, and in which the data bits are stored in the memory cells. A method for reading data bits from memory cells, in which the data bits have at least one byte-filling bit, where at least one predefined functionality for a subset of the data bits is coded in the at least one byte-filling bit, and in which the data bits are read from the memory cells based on the coded predefined functionality. Corresponding apparatuses and memories are also disclosed.