Abstract: What is specified is a method for transforming a first binary signal read from a memory, wherein the first binary signal is transformed into a second binary signal provided that the first binary signal is a code word or a predefined code word of a k-out-of-n code, wherein the first binary signal is transformed into a predefined signal provided that the first binary signal is not a code word or is not a predefined code word of the k-out-of-n code, wherein the predefined signal is different than the second binary signal. A corresponding device is furthermore specified.

Abstract: A method for data processing is disclosed. A blank state is determined for several data bits based on a majority decision. Each data bit is represented by a group of at least two memory cells. The at least two memory cells of this group are complementary cells of a differential read memory.

Abstract: A circuit arrangement for determining a correction signal on the basis of at least one bit error of a binary word is specified, including a plurality of subcircuits (ST), wherein a respective subcircuit is provided for a bit position to be corrected of the binary word, wherein each of the subcircuits provides at least two locator polynomial values, and comprising a selection unit, which determines a correction signal depending on the locator polynomial values and depending on an error signal (err, E). A method for driving such a circuit arrangement is furthermore proposed.

Abstract: A method for compensating for a read error is disclosed, wherein each of n states are read from memory cells of a memory, the states being determined in a time domain. If the n states do not form a code word of a k-from-n code, a plurality of states from the n states, which were determined within a reading window, are provided with a first valid assignment and fed to an error processing stage. If the error processing does not indicate an error, the n states are further processed with the first valid assignment, and if the error processing indicates an error, the plurality of states that were determined within the reading window are provided with a second valid assignment and the n states are further processed with the second valid assignment. Accordingly, a device, a system and a computer program product are also disclosed.

Abstract: A method is suggested for updating a memory comprising a first memory area and a second memory area, the method comprising the steps: (a) using a first image of data that is stored in the first memory area while writing a second image of data to the second memory area; (b) switching to using the second image of data that is stored in the second memory area; (c) writing an inverse image of the second image to the first memory area; and (d) using the first memory area and the second memory area as a differential memory. Also, a corresponding device is provided.

Abstract: The disclosure proposes a circuit including a memory which has a multiplicity of memory cells, the memory having a first area and a second area, at least one memory cell comprising a part of the first area and a part of the second area, the first area having a lower reliability than the second area, and the circuit being set up in such a manner that first bits are stored in the first area and second bits are stored in the second area. A circuit for reading the memory and methods for writing to and reading the memory are also disclosed.

Abstract: Overheat and fire detection for aircraft systems includes an optical controller and a fiber optic loop extending from the optical controller. The fiber optic loop extends through one or more zones of the aircraft. An optical signal is transmitted through the fiber optic loop from the optical controller and is also received back at the optical controller. The optical controller analyzes the optical signal to determine the temperature, strain, or both experienced within the zones.

Abstract: A method is proposed for processing a data word, in which the data word comprises a first partial data word and a second partial data word, in which first checkbits are defined for the first partial data word, wherein the first partial data word and the first checkbits form a first codeword, in which second checkbits are defined for the second partial data word, wherein the second partial data word and the second checkbits form a second codeword, in which third checkbits are defined for the data word, wherein at least (i) the data word, (ii) a linking of the first checkbits with the second checkbits, and (iii) the third checkbits are parts of a third codeword.

Abstract: A computer-implemented method of generating faster and more efficient database query execution plans includes receiving a database query, generating an optimized query execution plan, and initiating execution of the optimized plan. Database can include table columns with associated column dictionaries. Database query can have statements with conditions. Generating the optimized query execution plan involves comparing contents of a column dictionary semantics of the statements, omitting statements which will always be TRUE and omitting conditions which will always be FALSE. Related apparatus, systems, techniques, methods and articles are also described.

Abstract: A method for reading memory cells from a memory is stated, inter alia, in which physical values are determined from a number of n memory cells, wherein n is at least three, in which the physical values are at least partially compared with one another, in which K different digital memory cell values are assigned to the n memory cells on the basis of the compared physical values, and in which a code word of an n1-, . . . , nK-out-of-n code is assigned to the digital memory cell values obtained in this manner. In particular, the following apply in this case: n?3, n1?1 to nK?1, K?2 and m?1.

Abstract: The disclosure proposes a circuit including a memory which has a multiplicity of memory cells, the memory having a first area and a second area, at least one memory cell comprising a part of the first area and a part of the second area, the first area having a lower reliability than the second area, and the circuit being set up in such a manner that first bits are stored in the first area and second bits are stored in the second area. A circuit for reading the memory and methods for writing to and reading the memory are also disclosed.

Abstract: A solution is proposed for processing data bits, in which the data bits are transformed into first data bytes by means of a first transformation, in which the first data bytes are stored in a memory, in which second data bytes are read from the memory, in which each of the second data bytes, when there is no error, is a codeword of a block error code and in which one error signal per second data byte is determined that indicates whether or not this second data byte is a codeword.

Abstract: Overheat and fire detection for aircraft systems includes an optical controller and a fiber optic loop extending from the optical controller. The fiber optic loop extends through one or more zones of the aircraft. An optical signal is transmitted through the fiber optic loop from the optical controller and is also received back at the optical controller. The optical controller analyzes the optical signal to determine the temperature, strain, or both experienced within the zones.

Abstract: In various embodiments, a memory controller is provided. The memory controller may be configured to store data to a first memory portion of a memory, and to store at least one of error detection data or error correction data to be stored to a second memory portion of the memory, wherein the at least one of error detection data or the error correction data are associated with the data, and wherein the memory controller comprises a memory size assigning circuit configured to flexibly assign a size of the second memory portion.

Abstract: A centering device for centering a sliding door or window, including a rail; a moving member configured to be movable along the rail; and a plurality of centering rollers fixed to one of the rail and the moving member and spaced along a length thereof corresponding to a direction of movement of the door or window along the rail, the centering rollers abutting against an other of the rail and the moving member to laterally center the moving member with respect to the rail. The centering device can be implemented in a sill, header and jamb.

Abstract: A sliding roller assembly includes a plurality of blocks, configured to be connected in series, at least one roller device provided between each of the plurality of blocks, where the roller device includes a main body having at least one roller bearing disposed in the main body.

Abstract: A memory system having a flexible read reference is disclosed. The system includes a memory partition, a failcount component, and a controller. The memory partition includes a plurality of memory cells. The failcount component is configured to generate failcounts in response to read operations of the memory partition. The controller is configured to calibrate a reference value for the memory partition by utilizing the failcounts.

Abstract: Systems, apparatuses, and methods of and for an ophthalmic illuminated infusion line are provided. An example ophthalmic illuminated infusion line may include an infusion arrangement having a first flexible elongate member and a flow tube. The first flexible elongate member may have a lumen configured to deliver a fluid to an eye of a patient during a surgical procedure. The flow tube may be sized to penetrate the eye of the patient and deliver the fluid to an interior of an eye to maintain intraocular pressure during a surgical procedure. The ophthalmic illuminated infusion line may also include an optical fiber coupled to the infusion arrangement and configured to penetrate the eye of the patient with the flow tube and transmit light to illuminate the interior of the eye during the surgical procedure at the same time that the flow tube delivers the fluid to the interior of the eye.

Abstract: An illuminated microsurgical instrument is provided herein that includes a microsurgical instrument having a tubular member arranged to treat patient tissue at a surgical site, the tubular member having a distal tip, an inner surface, and an outer surface. The inner surface defines a lumen. The outer surface has a notch formed therein. The illuminated microsurgical instrument further includes an optical fiber arranged to deliver light to the surgical site. The optical fiber includes a proximal end arranged to receive a light beam from a light source and also includes a curved distal end arranged to emit light adjacent to the distal tip. A portion of the curved distal end is positioned within the notch and curves away from the tubular member.

Abstract: A circuit arrangement for determining in parallel of at least two byte error position signals for identifying at least one byte error in a binary sequence comprising a plurality of bytes, wherein the binary sequence in the error-free case is a code word of an error code, the circuit arrangement is configured such that each of the at least two byte error position signals is determinable using components of an error syndrome of the error code such that the components indicate whether or not a byte of the binary sequence that is associated with the byte error position signal is erroneous.