Abstract: An angled guide plate for fastening rails for rail vehicles to a tie using a tension spring that can be supported on the angled guide plate includes at least one support face, in particular a support shoulder, formed on a top side of the angled guide plate, for supporting the tension spring, a rail-side contact face for a rail foot of the rail, and an underside, on the opposite side from the top side, for supporting the angled guide plate on the tie. Formed on the underside is a rib which can be received movably in a groove formed in the tie, wherein a guide face extending at an acute angle to the rail-side contact face is provided such that, as a result of the rib moving in the groove, an adjustment of the rail-side contact face with a direction component extending perpendicularly to the contact face can be effected.

Abstract: A method and a dual beam device for three-dimensional volume image generation of semiconductor objects within a wafer can provide higher accuracy. The method and device can be configured to mitigate drifts between a charge-particle beam imaging system and a wafer stage by monitoring displacement vectors and considering the displacement vectors during 3D pixel interpolation from a plurality of two-dimensional cross section images.

Abstract: An apparatus for calibrating or validating performance of a computed tomography (CT) scanner including a first element having a first diameter, a second element having a base structure and a first set of test objects that can be coupled to the base structure and separated from one another by a first set of distances. The apparatus also includes a third element having a second diameter and a first length, a fourth element having a first face and a second face parallel to one another with a first depth defined there between.

Abstract: A tension spring for holding down a track body element, such as a rail foot of a rail, including a U-shaped main section which has a U-bend, a first leg arranged on one side of the U-bend and a second leg arranged on the other side of the U-bend, wherein a hook-shaped inwardly bent holding section which can be braced against a hold-down device is formed on the first leg and an end section bent towards or away from the holding section is formed on the second leg, wherein the U-bend forms a torsion section so that a hold-down force can be applied to the track body element via the bent end section.

Abstract: A method for monitoring a refrigerant fill-quantity of a refrigeration machine, which includes a compressor for compressing the refrigerant, an expansion device for relieving the pressure of the refrigerant, a high-pressure heat exchanger through which the refrigerant is passed after compression by the compressor to transfer heat to a heat ex-change medium, and a low-pressure heat exchanger through which the refrigerant is passed after pressure relief by the expansion device, to absorb heat from the heat ex-change medium or a further heat exchange medium. Fill level information relating to the refrigerant fill-quantity is determined as a function of a plurality of operating parameters, the fill level information is determined independently from the temperature of the refrigerant after compression by the compressor.

Abstract: A tension spring for holding down a track body element, such as a rail foot of a rail, including a U-shaped main section which has a U-bend, a first leg arranged on one side of the U-bend and a second leg arranged on the other side of the U-bend, wherein a hook-shaped inwardly bent holding section which can be braced against a hold-down device is formed on the first leg and an end section bent towards or away from the holding section is formed on the second leg, wherein the U-bend forms a torsion section so that a hold-down force can be applied to the track body element via the bent end section.

Abstract: Wireless circuitry may include phase-locked loop (PLL) circuitry. The PLL circuitry can include a time-to-digital converter (TDC) having a first input configured to receive a reference clock signal, a second input configured to receive a feedback clock signal, and an output at which a measured phase error is produced, a frequency divider configured to output the feedback clock signal, and a phase alignment circuit configured to output a corrected phase error that is used in adjusting the frequency divider. The phase alignment circuit can include a scaling component configured to scale the measured phase error by a phase alignment coefficient to produce a corresponding scaled phase error and a multiplexing component configured to selectively output a corrected phase error that is used in controlling a sigma delta modulator coupled to the divider.

Abstract: Communication circuitry may be provided with a self-injection locking loop that generates a signal. The loop may include an oscillator, a resonator coupled the oscillator over a first signal path, a square law device, a second signal path that couples a node on the first signal path to the square law device, a phase shifter on the second signal path, and a controller that couples the square law device to the oscillator. A portion of the signal may reflect off the resonator and back towards the oscillator to self-injection lock the oscillator to the resonator. The square law device may generate an electrical signal based on a filtered version of the signal produced by the resonator and a phase-shifted version of the signal produced by the phase shifter. The controller may adjust the oscillator based on the electrical signal to maintain the self-injection locking even as temperature changes over time.

Abstract: An electronic device may include wireless circuitry with first and second mixers on a signal path for converting a signal using first and second clock signals via high side injection (HSI) or low side injection (LSI). A first phase-locked loop (PLL) may generate the first clock signal and a second PLL may generate the second clock signal. A switch may couple the first PLL to a reference oscillator when LSI is used and may couple the first PLL to a third PLL when HSI is used. The third PLL may generate a second reference signal based on a first reference signal from the reference oscillator. The second PLL may generate the second clock signal based on the output of the third PLL. This may serve to may minimize phase noise even as the mixers switch between HSI and LSI.

Abstract: A support sleeve assembly (1) for fastening on a cable (5), in particular on an electrical cable (5) for high-voltage engineering, has an external element (2) which is formed from a metal sheet, and at least one adapter element (3) comprising a plastics material. The external element (2) is formed so as to be at least partially annular. The at least one adapter element (3) is received within the external element (2) and is captively fastened to the external element (2).

Abstract: To enhance phase-locked loop (PLL) performance, PLL duty-cycle calibration may be desirable. In some cases, higher reference clock frequency may assist in reducing phase noise and increasing power efficiency of the PLL. A frequency doubler may increase the PLL reference clock frequency, but the duty cycle error in the clock may result in a spur at a clock frequency offset. Low phase noise PLL architectures may include a static phase offset at the PLL input between the reference path and the feedback path, and the static phase offset may vary with PVT, which may limit the accuracy of duty cycle error detection. Correcting for the static phase offset may cause a disturbance at the PLL output. To address the duty cycle error caused by the higher reference clock frequency, a duty cycle calibration loop may be introduced. For the duty cycle calibration loop, the phase offset information for even clock instances and odd clock instances may be extracted.

Abstract: To enhance phase-locked loop (PLL) performance, PLL duty-cycle calibration may be desirable. In some cases, higher reference clock frequency may assist in reducing phase noise and increasing power efficiency of the PLL. A frequency doubler may increase the PLL reference clock frequency, but the duty cycle error in the clock may result in a spur at a clock frequency offset. Low phase noise PLL architectures may include a static phase offset at the PLL input between the reference path and the feedback path, and the static phase offset may vary with PVT, which may limit the accuracy of duty cycle error detection. Correcting for the static phase offset may cause a disturbance at the PLL output. To address the duty cycle error caused by the higher reference clock frequency, a duty cycle calibration loop may be introduced. For the duty cycle calibration loop, phase offset information may be extracted.

Abstract: A seat may have a seat longitudinal adjustment device having two rail pairs. The rail pairs may each have a lower rail and an upper rail. A contacting device is provided at least for electrically connecting a drive unit and a number of seat components to at least one control unit and to an electrical power supply unit. The contacting device may have at least one plug having a number of contact pins and/or contact elements, and a socket having a number of corresponding mating contact elements. When the plug is inserted into the socket, at least the electrical connection is established between the electrical power supply unit and the at least one control unit and the drive unit for the seat longitudinal adjustment device and the seat components. The contacting device may have at least one positioning element and/or one short-circuit element.

Abstract: An optical device is formed by hot stamping a demetallized hologram to an optically variable foil or to a coating of optically variable ink. In another embodiment a hologram is hot stamped to a banknote or document printed with a color-shifting ink.

Abstract: A valve (1) with a valve housing (2) and valve openings (3), and with a closing element (5) and at least one valve drive (6). The valve also has two mutually opposite flanges (9, 10) each having a passage opening (11). The flanges can be moved towards and away from one another by the valve drive and are force-coupled to the closing element with respect to the movements of the closing element and in the fully opened position of the closing element are pressed against the wall regions (4) of the valve housing and thus the passage openings of the flanges connect the valve openings together. The two flanges (9, 10) each include a sequence of fingers (12) and recesses (13) arranged in between, and the fingers surround the passage openings and the fingers of the one flange engage in the respective recesses of the other flange.

Abstract: An electronic device may include wireless circuitry with first and second mixers on a signal path for converting a signal using first and second clock signals via high side injection (HSI) or low side injection (LSI). A first phase-locked loop (PLL) may generate the first clock signal and a second PLL may generate the second clock signal. A switch may couple the first PLL to a reference oscillator when LSI is used and may couple the first PLL to a third PLL when HSI is used. The third PLL may generate a second reference signal based on a first reference signal from the reference oscillator. The second PLL may generate the second clock signal based on the output of the third PLL. This may serve to may minimize phase noise even as the mixers switch between HSI and LSI.

Abstract: This disclosure is directed to PLLs, and, in particular, to enhancing PLL performance via gain calibration. PLL loop gain may vary with respect to process, voltage, and temperature (PVT) variation. To control the PLL loop gain, a gain calibration loop may be implemented. However, calibrating the loop gain by directly measuring the loop gain may be disadvantageous. To reduce or eliminate PLL loop gain variation due to PVT variation, a PLL having a loop gain function that is a function of an input phase offset time with a phase noise performance that remains consistent across PVT variations is disclosed. By determining a relationship between PLL loop gain and phase offset, detecting and calibrating phase offset may result in enhanced calibration of the PLL loop gain, while avoiding the additional difficulty and complexity associated with directly measuring loop gain of a PLL.

Abstract: This disclosure is directed to enhancing PLL performance via gain calibration and duty cycle calibration. It may be desirable to perform loop gain and duty cycle calibration simultaneously. However, doing so may result in prohibitive complexity and/or area/power penalty. To enable loop gain calibration and duty cycle calibration simultaneously, the duty cycle error and the gain error may be detected in the time domain, which may enable duty cycle calibration and loop gain calibration circuitries to share a phase detector. Detecting the duty cycle error and the loop gain error in the time domain may be accomplished by implementing an analog or digital PLL system, wherein the loop gain of the PLL system is a function of the input phase offset time.

Abstract: An apparatus for calibrating or validating performance of a computed tomography (CT) scanner including a first element having a first diameter, a second element having a base structure and a first set of test objects that can be coupled to the base structure and separated from one another by a first set of distances. The apparatus also includes a third element having a second diameter and a first length, a fourth element having a first face and a second face parallel to one another with a first depth defined there between.

Abstract: To enhance phase-locked loop (PLL) performance, PLL duty-cycle calibration may be desirable. In some cases, higher reference clock frequency may assist in reducing phase noise and increasing power efficiency of the PLL. A frequency doubler may increase the PLL reference clock frequency, but the duty cycle error in the clock may result in a spur at a clock frequency offset. Low phase noise PLL architectures may include a static phase offset at the PLL input between the reference path and the feedback path, and the static phase offset may vary with PVT, which may limit the accuracy of duty cycle error detection. Correcting for the static phase offset may cause a disturbance at the PLL output. To address the duty cycle error caused by the higher reference clock frequency, a duty cycle calibration loop may be introduced. For the duty cycle calibration loop, phase offset information may be extracted.