Patents by Inventor Thomas Parnell

Thomas Parnell has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200356893
    Abstract: Parallel training of a machine learning model on a computerized system may be provided. Computing tasks can be assigned to multiple workers of a system. A method may include accessing training data. A parallel training of the machine learning model can be started based on the accessed training data, so as for the training to be distributed through a first number K of workers, K>1. Responsive to detecting a change in a temporal evolution of a quantity indicative of a convergence rate of the parallel training (e.g., where said change reflects a deterioration of the convergence rate), the parallel training of the machine learning model is scaled-in, so as for the parallel training to be subsequently distributed through a second number K? of workers, where K>K??1. Related computerized systems and computer program products may be provided.
    Type: Application
    Filed: May 7, 2019
    Publication date: November 12, 2020
    Inventors: Michael Kaufmann, Thomas Parnell, Antonios Kornilios Kourtis
  • Patent number: 10797723
    Abstract: A technique for selecting context models (CMs) for a CM ensemble (CME) in a context mixing compressor includes measuring compression ratios (CRs) of the compressor on a dataset for each CM included in a base set of CMs. A first CM that has a maximum CR for the dataset is added to the CME. In response to a desired number of the CMs not being in the CME, subsequent CRs for the compressor are measured on the dataset for each of the CMs in the base set of CMs that are not in the CME in conjunction with one or more CMs in the CME. In response to a desired number of the CMs not being in the CME, subsequent CMs that in conjunction with the one or more CMs in the CME result in a maximum subsequent CR for the dataset are added to the CME.
    Type: Grant
    Filed: March 14, 2017
    Date of Patent: October 6, 2020
    Assignee: International Business Machines Corporation
    Inventors: Tobias Blaettler, Thomas Mittelholzer, Thomas Parnell, Charalampos Pozidis
  • Patent number: 10732846
    Abstract: A computer-implemented method according to one embodiment includes determining, after writing data to a non-volatile memory block, one or more delta threshold voltage shift (TVS?) values. One or more overall threshold voltage shift values for the data written to the non-volatile memory block are calculated, the values being a function of the one or more TVS? values to be used when writing data to the non-volatile memory block. The overall threshold voltage shift values are stored. A base threshold voltage shift (TVSBASE) value, the one or more TVS? values, or both the TVSBASE value and the one or more TVS? values are re-calibrated during a background health check after a predetermined number of background health checks without calibration are performed.
    Type: Grant
    Filed: January 9, 2019
    Date of Patent: August 4, 2020
    Assignee: International Business Machines Corporation
    Inventors: Charles J. Camp, Timothy J. Fisher, Aaron D. Fry, Nikolas Ioannou, Ioannis Koltsidas, Nikolaos Papandreou, Thomas Parnell, Roman A. Pletka, Charalampos Pozidis, Sasa Tomic
  • Patent number: 10700702
    Abstract: In a data storage system, a prior set S of prefix codes for pseudo-dynamic compression as well as data compressed utilizing prior set S are stored. While data compressed utilizing prior set S are stored in the data storage system, the number of prefix codes utilized by the data storage system for pseudo-dynamic compression are augmented. Augmenting the number of codes includes determining a new set S? of prefix codes for pseudo-dynamic compression from a training data set selected from a workload of the data storage system and storing the new set S? in the data storage system with the prior set S.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: June 30, 2020
    Assignee: International Business Machines Corporation
    Inventors: Charles J. Camp, Charalampos Pozidis, Nikolaos Papandreou, Roman A. Pletka, Thomas Mittelholzer, Thomas Parnell, Tobias Blaettler
  • Publication number: 20200184368
    Abstract: Computer-implemented methods are provided for implementing training of a machine learning model in a heterogeneous processing system that includes a host computer operatively interconnected to an accelerator unit. The training operation involves an iterative optimization process for optimizing a model vector defining the model. Such a method includes, in the host computer, storing a matrix of training data and partitioning the matrix into a plurality of batches of data vectors. For each of successive iterations of the optimization process, a selected subset of the batches is provided to the accelerator unit. In the accelerator unit, each iteration of the optimization process is performed to update the model vector in dependence on vectors in the selected subset for that iteration. In the host computer, batch importance values are calculated for respective batches. The batch importance value is dependent on contributions of vectors in that batch to sub-optimality of the model vector.
    Type: Application
    Filed: December 10, 2018
    Publication date: June 11, 2020
    Inventors: Celestine Duenner, Thomas Parnell, Charalampos Pozidis
  • Publication number: 20200184369
    Abstract: Computer-implemented methods are provided for implementing training of a machine learning model in a heterogeneous processing system comprising a host computer operatively interconnected with an accelerator unit. The training includes a stochastic optimization process for optimizing a function of a training data matrix X, having data elements Xi,j with row coordinates i=1 to n and column coordinates j=1 to m, and a model vector w having elements wj. For successive batches of the training data, defined by respective subsets of one of the row coordinates and column coordinates, random numbers associated with respective coordinates in a current batch b are generated in the host computer and sent to the accelerator unit. In parallel with generating the random numbers for batch b, batch b is copied from the host computer to the accelerator unit.
    Type: Application
    Filed: December 10, 2018
    Publication date: June 11, 2020
    Inventors: Thomas Parnell, Celestine Duenner, Charalampos Pozidis, Dimitrios Sarigiannis
  • Patent number: 10615824
    Abstract: Symbols are loaded into a diagonal anti-diagonal structure. To provide for fast loading, the symbols may be shifted by one or more shift registers associated with the diagonal or anti-diagonal structure. The two locations at which each symbol are positioned are included within different diagonals or anti-diagonals making it possible to load or unload either symbol or multiple symbols in a single clock cycle. Further, by partitioning the diagonal anti-diagonal structure, multiple respective symbols or plurality of symbols may be loaded or unloaded in a single clock cycle.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: April 7, 2020
    Assignee: International Business Machines Corporation
    Inventors: Tobias Blaettler, Charles J. Camp, Thomas Mittelholzer, Nikolaos Papandreou, Thomas Parnell, Charalampos Pozidis
  • Publication number: 20200104276
    Abstract: Methods are provided for implementing training of a machine learning model in a processing system, together with systems for performing such methods. A method includes providing a core module for effecting a generic optimization process in the processing system, and in response to a selective input, defining a set of derivative modules, for effecting computation of first and second derivatives of selected functions ƒ and g in the processing system, to be used with the core module in the training operation. The method further comprises performing, in the processing system, the generic optimization process effected by the core module using derivative computations effected by the derivative modules.
    Type: Application
    Filed: September 27, 2018
    Publication date: April 2, 2020
    Inventors: Thomas Parnell, Celestine Duenner, Dimitrios Sarigiannis, Charalampos Pozidis
  • Patent number: 10592110
    Abstract: A technique for adapting over-provisioning space in a storage system includes determining one or more workload characteristics in the storage system. Over-provisioning space in the storage system is then adjusted to achieve a target write amplification for the storage system, based on the workload characteristics.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: March 17, 2020
    Assignee: International Business Machines Corporation
    Inventors: Charles J. Camp, Timothy J. Fisher, Aaron D. Fry, Nikolas Ioannou, Thomas Parnell, Roman A. Pletka, Sasa Tomic
  • Patent number: 10528424
    Abstract: A computer-implemented method, according to one embodiment, includes: detecting at least one read of a logical page straddled across codewords, storing an indication of a number of detected reads of the straddled logical page, and relocating the straddled logical page to a different physical location in response to the number of detected reads of the straddled logical page. When relocated, the logical page is written to the different physical location in a non-straddled manner. Other systems, methods, and computer program products are described in additional embodiments.
    Type: Grant
    Filed: October 19, 2017
    Date of Patent: January 7, 2020
    Assignee: International Business Machines Corporation
    Inventors: Charles J. Camp, Timothy J. Fisher, Nikolas Ioannou, Thomas Parnell, Roman A. Pletka, Sasa Tomic
  • Patent number: 10417088
    Abstract: A data protection technique combines error correcting code and redundant array of independent disk functionality for a non-volatile memory (NVM) array of a data storage system. The technique includes receiving, by a controller, data for storage in the NVM. In response to receiving the data for storage in the NVM array, the controller forms first component codewords based on encodings with a first level code of respective first portions of the data. In response to receiving the data for storage in the NVM array, the controller forms a second component codeword based on an encoding with a second level code of a second portion of the data and the first component codes. The controller stores a respective portion of each of the first and second component codeswords on packages of the NVM array. The storing achieves maximum equal spreading of each of the component codewords across all of the packages.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: September 17, 2019
    Inventors: Timothy J. Fisher, Thomas Mittelholzer, Nikolaos Papandreou, Thomas Parnell, Charalampos Pozidis, Andrew D. Walls
  • Patent number: 10361712
    Abstract: A technique for non-binary context mixing in a compressor includes generating, by a plurality of context models, model predictions regarding a value of a next symbol to be encoded. A mixer generates a set of final predictions from the model predictions. An arithmetic encoder generates compressed data based on received input symbols and the set of final predictions. The received input symbols belong to an alphabet having a size greater than two and the mixer generates a feature matrix from the model predictions and trains a classifier that generates the set of final predictions.
    Type: Grant
    Filed: March 14, 2017
    Date of Patent: July 23, 2019
    Assignee: International Business Machines Corporation
    Inventors: Tobias Blaettler, Thomas Mittelholzer, Thomas Parnell, Charalampos Pozidis
  • Patent number: 10348334
    Abstract: A decoder performs iterative decoding of a codeword encoded by a binary symmetry-invariant product code, such as a half product code or quarter product code. In response to the iterative decoding reaching a stopping set, the decoder determines by reference to an ambient error graph formed from the stopping set whether or not the stopping set is correctable by post-processing. If not, the decoder outputs the uncorrected codeword and signals a decoding failure. In response to determining that the stopping set is correctable by post-processing, the decoder inverts all bits of the codeword corresponding to edges of the ambient error graph, applies an additional round of iterative decoding to the codeword to obtain a corrected codeword, and outputs the corrected codeword. Post-processing in this manner substantially lowers an error floor associated with the binary symmetry-invariant product code.
    Type: Grant
    Filed: October 25, 2016
    Date of Patent: July 9, 2019
    Assignee: International Business Machines Corporation
    Inventors: Tobias Blaettler, Thomas Mittelholzer, Nikolaos Papandreou, Thomas Parnell, Charalampos Pozidis
  • Patent number: 10310938
    Abstract: Techniques for data deduplication in a data storage system include comparing a first attribute of a received data page to first attributes of one or more stored data pages. In response to the first attribute matching one of the first attributes, a second attribute of the received data page is compared to second attributes of the one or more data pages. In response to the second attribute of the received data page matching one of the second attributes, a fingerprint of the received data page is compared to fingerprints of the one or more data pages. In response to the fingerprint of the received data page matching one of the fingerprints, the received data page is discarded and replaced with a reference to the corresponding data page already stored in the storage system. In response to first attribute, the second attribute, or the fingerprint of the received data page not matching, the received data page is stored.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: June 4, 2019
    Assignee: International Business Machines Corporation
    Inventors: Timothy J. Fisher, Nikolas Ioannou, Thomas Parnell, Roman A. Pletka, Sasa Tomic
  • Publication number: 20190146671
    Abstract: A computer-implemented method according to one embodiment includes determining, after writing data to a non-volatile memory block, one or more delta threshold voltage shift (TVS?) values. One or more overall threshold voltage shift values for the data written to the non-volatile memory block are calculated, the values being a function of the one or more TVS? values to be used when writing data to the non-volatile memory block. The overall threshold voltage shift values are stored. A base threshold voltage shift (TVSBASE) value, the one or more TVS? values, or both the TVSBASE value and the one or more TVS? values are re-calibrated during a background health check after a predetermined number of background health checks without calibration are performed.
    Type: Application
    Filed: January 9, 2019
    Publication date: May 16, 2019
    Inventors: Charles J. Camp, Timothy J. Fisher, Aaron D. Fry, Nikolas Ioannou, Ioannis Koltsidas, Nikolaos Papandreou, Thomas Parnell, Roman A. Pletka, Charalampos Pozidis, Sasa Tomic
  • Publication number: 20190138390
    Abstract: A data protection technique combines error correcting code and redundant array of independent disk functionality for a non-volatile memory (NVM) array of a data storage system. The technique includes receiving, by a controller, data for storage in the NVM. In response to receiving the data for storage in the NVM array, the controller forms first component codewords based on encodings with a first level code of respective first portions of the data. In response to receiving the data for storage in the NVM array, the controller forms a second component codeword based on an encoding with a second level code of a second portion of the data and the first component codes. The controller stores a respective portion of each of the first and second component codeswords on packages of the NVM array. The storing achieves maximum equal spreading of each of the component codewords across all of the packages.
    Type: Application
    Filed: November 9, 2017
    Publication date: May 9, 2019
    Inventors: TIMOTHY J. FISHER, THOMAS MITTELHOLZER, NIKOLAOS PAPANDREOU, THOMAS PARNELL, CHARALAMPOS POZIDIS, ANDREW D. WALLS
  • Patent number: 10268537
    Abstract: In at least one embodiment, a history data structure of a Lempel-Ziv compressor is preloaded with fixed predetermined history data typical of actual data of a workload of the Lempel-Ziv compressor. The Lempel-Ziv compressor then compresses each of multiple data pages in a sequence of data pages by reference to the fixed predetermined history data.
    Type: Grant
    Filed: May 26, 2016
    Date of Patent: April 23, 2019
    Assignee: International Business Machines Corporation
    Inventors: Tobias Blaettler, Thomas Mittelholzer, Nikolaos Papandreou, Thomas Parnell, Charalampos Pozidis
  • Patent number: 10236067
    Abstract: A controller adapts the read voltage thresholds of a memory unit in a non-volatile memory. In one embodiment, the controller determines, based on statistics for a memory unit of the non-volatile memory, an operating state of the memory unit from among a plurality of possible operating states and adapts at least one read voltage threshold for a memory cell in the memory unit based on the determined operating state.
    Type: Grant
    Filed: August 2, 2017
    Date of Patent: March 19, 2019
    Assignee: International Business Machines Corporation
    Inventors: Timothy J. Fisher, Thomas Mittelholzer, Nikolaos Papandreou, Thomas Parnell, Charalampos Pozidis
  • Patent number: 10222997
    Abstract: A computer program product according to one embodiment includes a computer readable storage medium having program instructions embodied therewith. The program instructions are executable by a processing circuit to cause the circuitry to perform a method including determining, after writing data to a non-volatile memory block, one or more delta threshold voltage shift (TVS?) values. One or more overall threshold voltage shift values for the data written to the non-volatile memory block are calculated, the values being a function of the one or more TVS? values to be used when writing data to the non-volatile memory block. The overall threshold voltage shift values are stored. A base threshold voltage shift (TVSBASE) value, the one or more TVS? values, or both the TVSBASE value and the one or more TVS? values are re-calibrated during a background health check after a predetermined number of background health checks without calibration are performed.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: March 5, 2019
    Assignee: International Business Machines Corporation
    Inventors: Charles J. Camp, Timothy J. Fisher, Aaron D. Fry, Nikolas Ioannou, Ioannis Koltsidas, Nikolaos Papandreou, Thomas Parnell, Roman A. Pletka, Charalampos Pozidis, Sasa Tomic
  • Patent number: 10222998
    Abstract: In one embodiment, a computer program product includes a computer readable storage medium having program instructions embodied therewith. The program instructions are executable by a processing circuit to cause the processing circuit to perform a method that includes determining, after writing data to a non-volatile memory block, one or more delta threshold voltage shift (TVS?) values. One or more overall threshold voltage shift values is calculated for the data written to the non-volatile memory block. The one or more overall threshold voltage shift values are stored. The method also includes reading one or more TVS values from a non-volatile controller memory, and resetting a program/erase cycle count since last calibration after calibrating the one or more overall threshold voltage shift values. The one or more TVS? values and the program/erase cycle count since last calibration are stored to the non-volatile controller memory.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: March 5, 2019
    Assignee: International Business Machines Corporation
    Inventors: Charles J. Camp, Timothy J. Fisher, Aaron D. Fry, Nikolas Ioannou, Ioannis Koltsidas, Nikolaos Papandreou, Thomas Parnell, Roman A. Pletka, Charalampos Pozidis, Sasa Tomic