Abstract: A multidimensional storage array includes independently addressable storage elements and an input shifter. The storage elements are physically arranged into rows and columns and store particular bit(s) of a data word. The input shifter implements a circular shift to serially loaded data words to the multidimensional storage array. An output shifter may reverse the circular shift of a requested data word. The data entering the storage array may be shifted to expose column addressed data such that an entire column or columns may be fed to a requesting device in a single hardware clock cycle and/or may be shifted to expose row addressed data such that an entire row or rows may be fed to the requesting device in a single hardware clock cycle. The data entering the storage array may be shifted such that column addressed data words may be stored in a plurality of diagonally arranged storage elements.

Abstract: A technique for operating a data storage system that includes a non-volatile memory array controlled by a controller includes storing, in the non-volatile memory array, first data whose frequency of access is above a first access level in a bandwidth optimized code word. Second data whose frequency of access is below a second access level is stored in the non-volatile memory in a code rate optimized code word.

Abstract: A quarter product code codeword includes various R code symbols and C code symbols each including a plurality of symbols. Each symbol is loaded into a diagonal anti-diagonal structure in two unique locations. To provide for fast loading, the symbols may be shifted by one or more shift registers associated with the diagonal or anti-diagonal structure. The two locations at which each symbol is positioned are included within different diagonals or anti-diagonals making it possible to load or unload either symbol or multiple symbols in a single clock cycle. Further, by partitioning the diagonal anti-diagonal structure, multiple respective symbols or plurality of symbols may be loaded or unloaded in a single clock cycle.

Abstract: In a data storage system including a non-volatile memory array, a controller repeatedly determines at least one health metric of the non-volatile memory array during an operating lifetime of the non-volatile memory array. In response to determining the at least one health metric, the controller selectively varies an erase parameter of the non-volatile memory array over the operating lifetime of the non-volatile memory array, such that endurance of the non-volatile memory array is improved.

Abstract: According to one embodiment, a method includes assigning a subset of physical pages within a block of non-volatile memory to a pseudo-physical block, wherein a number of pages in the pseudo-physical block is less than a number of physical pages within the non-volatile memory block, and reassigning physical pages within the block of non-volatile memory to the pseudo-physical block upon occurrence of an event. The assigning includes: determining a health metric for each of the physical pages within the block of non-volatile memory, and selecting a subset of the physical pages for assignment to the pseudo-physical block based on the health metric. Moreover, the subset of pages has a fixed size for at least a number of reassignments.

Abstract: A method, according to one embodiment, includes selecting, from a buffer, a combination of compressed logical pages of data to maximize an amount of used space in an error correction code container. The method also preferably includes processing the combination of compressed logical pages to generate error correction code data. Furthermore, the method may include writing the data corresponding to the combination of compressed logical pages and the associated error correction code data to a non-volatile random access memory. Other systems, methods, and computer program products are described in additional embodiments.

Abstract: A multidimensional storage array system includes storage elements arranged in storage array partitions, multiple input shifters, and multiple output shifters. A particular input shifter and output shifter is associated with a particular storage array partition. The storage elements are physically arranged into rows and columns and each store particular bit(s) of a data word. The input shifter implements a positional shift to loaded data words to the associated partition. The output shifter reverses the shift of a received shifted data word that is requested by a requesting device such as a decoder. The shifted data words in the storage array expose, for example, row addressed data words or column addressed data word sections so that multiple row or column addressed data words may be unloaded from the array simultaneously in a single hardware clock cycle.

Abstract: In one embodiment, a computer-implemented method includes determining, by a processor, after the writing of data to a non-volatile memory block, one or more delta threshold voltage shift (TVS?) values configured to track temporary changes with respect to changes in the underlying threshold voltage distributions due to retention and/or read disturb errors. One or more overall threshold voltage shift values is calculated for the data written to the non-volatile memory block, the one or more overall threshold voltage shift values being a function of the one or more TVS? values to be used when writing data to the non-volatile memory block. The one or more overall threshold voltage shift values are stored.

Abstract: In one embodiment, an apparatus includes one or more memory devices, each memory device having non-volatile memory configured to store data, and a memory controller connected to the one or more memory devices, the memory controller being configured to receive data to be stored to the one or more memory devices, store read-hot data within one error correction code (ECC) codeword as aligned data, and store read-cold data to straddle two or more ECC codewords as non-aligned data and/or dispersed data. According to another embodiment, a method for storing data to non-volatile memory includes receiving data to store to one or more memory devices, each memory device including non-volatile memory configured to store data, storing read-hot data within one ECC codeword as aligned data, and storing read-cold data to straddle two or more ECC codewords as non-aligned data and/or dispersed data.

Abstract: A multi-chip device and method for storing input data. The multi-chip device includes: a plurality of memory chips being adapted to store encoded input data, wherein each of the plurality of memory chips includes a detection unit that outputs detection information; an evaluation unit being adapted to perform an evaluation of the detection information from each of the plurality of memory chips, and to adapt the detection algorithm of any of the detection units depending on the performed evaluation; a combination unit being adapted to receive the detected bits and to combine the detected bits; and a decoding unit being adapted to output decoded data by decoding the combined detected bits. The present invention also provides a method and a computer program product for storing input data.

Abstract: A device for storing data in a plurality of multi-level cell memory chips. The device includes a scrambling unit to generate a plurality of candidate scrambled sequences of data by performing a plurality of scrambling operations on a sequence of data to be stored, a calculation unit to calculate a cost function for each of the plurality of candidate scrambled sequences of data, the result of each cost function being indicative of a balancing degree of subsequences of a candidate scrambled sequence, when the subsequences of the candidate scrambled sequence are written to the plurality of multi-level cell memory chips, a selection unit to select one of the candidate scrambled sequences of data based on the results of the cost functions, and a storing unit to store the selected candidate scrambled sequence of data in the multi-level cell memory chips by storing the subsequences across the multi-level memory chips.

Abstract: In one embodiment, a method for managing threshold voltage shifts in Flash memory includes determining, by a processor after writing data to a Flash memory block, base threshold voltage shift (TVSBASE) value(s) configured to track permanent changes in underlying threshold voltage distributions due to cycling of the Flash memory block, determining, after the writing of data to the Flash memory block, delta threshold voltage shift (TVS?) value(s) configured to track temporary changes, with respect to changes in the underlying threshold voltage distributions due to retention and/or read disturb errors, calculating an overall threshold voltage shift (TVS) value for the data written to the Flash memory block, the overall TVS value being a function of the TVSBASE and TVS? value(s) to be used when writing data to the Flash memory block, and applying the overall TVS value to a read operation of the data stored to the Flash memory block.

Abstract: Methods and apparatus 3 are provided for encoding data for storage in multilevel memory cells 2 having q cell-levels. Input data words are encoded into respective codewords, each having N symbols with one of q symbol-values, via an encoding scheme adapted such that the q symbol-values have unequal multiplicities within at least some codewords, and the multiplicity of each of the q symbol-values in every codeword is no less than ?, where ??2 and more preferably ?3. A first type of encoding scheme uses recursive symbol-flipping to enforce the ?-constraint, adding indicator symbols to indicate the flipped symbols. A second type of encoding scheme maps data words to codewords of a union of permutation codes, the initial vectors for these permutation codes being selected to enforce the ?-constraint. The N qary symbols of each codeword are supplied for storage in respective cells of the multilevel memory 2.

Abstract: Methods and apparatus are provided for determining level-thresholds for q-level memory cells. A group of the memory cells are read to obtain respective read signal components. The read signal components are processed in dependence on signal level to produce a signal level vector, comprising a series of elements, indicative of the distribution of read signal components in order of signal level. A plurality of possible sets of q?1 elements corresponding, respectively, to q?1 level-thresholds which partition the signal level vector into q segments, is then defined. The q?1 level-thresholds for the group of memory cells are then determined by selecting from said possible sets that set for which a predetermined difference function, dependent on differences in signal level for elements in each of said q segments for the set, has an optimum value.

Abstract: A data encoding method includes storing K input data symbols; assigning the symbols to respective symbol locations in a notional square array, having n rows and n columns of locations, to define a plurality of k-symbol words in respective rows; encoding the words by encoding rows and columns of the array dependent on a product code having identical row and column codes, each being a reversible error-correction code of dimension k and length n=2n?, thereby to define a codeword, having n2 code symbols corresponding to respective locations of the array, of a quarter product code defined by CQ={X?XT?(X?XT)F: X?C} where X is an n by n-symbol matrix defining a codeword of the product code, XT is the transpose matrix of X, and (X?XT)F is a reflection of matrix (X?XT) in the anti-diagonal thereof.

Abstract: A data encoding method includes storing K input data symbols; assigning the symbols to respective symbol locations in a notional square array, having n rows and n columns of locations, to define a plurality of k-symbol words in respective rows; encoding the words by encoding rows and columns of the array dependent on a product code having identical row and column codes, each being a reversible error-correction code of dimension k and length n=2n?, thereby to define a codeword, having n2 code symbols corresponding to respective locations of the array, of a quarter product code defined by CQ={X?XT?(X?XT)F:X?C} where X is an n by n-symbol matrix defining a codeword of the product code, XT is the transpose matrix of X, and (X?XT)F is a reflection of matrix (X?XT) in the anti-diagonal thereof.

Abstract: A technique for operating a data storage system that includes a non-volatile memory array controlled by a controller includes storing, in the non-volatile memory array, first data whose frequency of access is above a first access level in a bandwidth optimized code word. Second data whose frequency of access is below a second access level is stored in the non-volatile memory in a code rate optimized code word.

Abstract: In at least one embodiment, a controller of a non-volatile memory array determines, for each of a plurality of regions of physical memory in the memory array, an associated health grade among a plurality of health grades and records the associated health grade. The controller also establishes a mapping between access heat and the plurality of health grades. In response to a write request specifying an address, the controller selects a region of physical memory to service the write request from a pool of available regions of physical memory based on an access heat of the address and the mapping and writes data specified by the write request to the selected region of physical memory.

Abstract: Device for selecting a level for at least one read voltage for reading data stored in a multi-level memory device. The multi-level memory device includes a plurality of memory blocks, in which each of the memory blocks includes a plurality of word lines, each of the word lines being allocated to a plurality of memory pages and being indexed by a word line index. The device includes a first mapping unit for mapping each of the word line indices to one bin label, in which the number of bin labels is smaller than the number of word lines, and a second mapping unit for mapping each of the bin labels to a voltage information being indicative for at least one read voltage, in which the level for the at least one read voltage for reading data is selectable for each word line based on the respective word line index.

Abstract: A method for repairing a cast component having a damaged area is provided. The method includes scanning an area adjacent to the damaged area to create a scan. The method includes forming a dam with a void. The void has a profile corresponding to the scan. The method includes positioning the dam adjacent to the damaged area. The method includes heating the cast component. The method includes introducing a repair material into the dam. The method also includes cooling the cast component. The method further includes removing an excess material from the cast component.