Abstract: A device for storing data in a plurality of multi-level cell memory chips. The device includes a scrambling unit to generate a plurality of candidate scrambled sequences of data by performing a plurality of scrambling operations on a sequence of data to be stored, a calculation unit to calculate a cost function for each of the plurality of candidate scrambled sequences of data, the result of each cost function being indicative of a balancing degree of subsequences of a candidate scrambled sequence, when the subsequences of the candidate scrambled sequence are written to the plurality of multi-level cell memory chips, a selection unit to select one of the candidate scrambled sequences of data based on the results of the cost functions, and a storing unit to store the selected candidate scrambled sequence of data in the multi-level cell memory chips by storing the subsequences across the multi-level memory chips.

Abstract: In at least one embodiment, a non-volatile memory array including a plurality of blocks each including a plurality of physical pages is controlled by a controller. The controller implements a plurality of nested page retirement classes each defined by a respective one of a plurality of different nested subsets of page indices of physical pages within the plurality of blocks that are to be considered retired from use. For each block among the plurality of blocks, the controller updating an indication of a page retirement class to which the block belongs in response to detection of a retirement-causing error in a data page stored in a physical page of the block. The controller forms block stripes for storing data from the plurality of blocks based on the page retirement classes of the blocks.

Abstract: A quarter product code codeword includes various R code symbols and C code symbols each including a plurality of symbols. Each symbol is loaded into a diagonal anti-diagonal structure in two unique locations. To provide for fast loading, the symbols may be shifted by one or more shift registers associated with the diagonal or anti-diagonal structure. The two locations at which each symbol is positioned are included within different diagonals or anti-diagonals making it possible to load or unload either symbol or multiple symbols in a single clock cycle. Further, by partitioning the diagonal anti-diagonal structure, multiple respective symbols or plurality of symbols may be loaded or unloaded in a single clock cycle.

Abstract: A device for storing data in a plurality of multi-level cell memory chips. The device includes a scrambling unit to generate a plurality of candidate scrambled sequences of data by performing a plurality of scrambling operations on a sequence of data to be stored, a calculation unit to calculate a cost function for each of the plurality of candidate scrambled sequences of data, the result of each cost function being indicative of a balancing degree of subsequences of a candidate scrambled sequence, when the subsequences of the candidate scrambled sequence are written to the plurality of multi-level cell memory chips, a selection unit to select one of the candidate scrambled sequences of data based on the results of the cost functions, and a storing unit to store the selected candidate scrambled sequence of data in the multi-level cell memory chips by storing the subsequences across the multi-level memory chips.

Abstract: An apparatus, according to one embodiment, includes: one or more memory devices, each memory device comprising non-volatile memory configured to store data, and a memory controller connected to the one or more memory devices. The memory controller is configured to: detect at least one read of a logical page straddled across codewords, store an indication of a number of detected reads of the straddled logical page, and relocate the straddled logical page to a different physical location in response to the number of detected reads of the straddled logical page, wherein the logical page is written to the different physical location in a non-straddled manner. Other systems, methods, and computer program products are described in additional embodiments.

Abstract: A quarter product code codeword includes various R code symbols and C code symbols each including a plurality of symbols. Each symbol is loaded into a diagonal anti-diagonal structure in two unique locations. To provide for fast loading, the symbols may be shifted by one or more shift registers associated with the diagonal or anti-diagonal structure. The two locations at which each symbol is positioned are included within different diagonals or anti-diagonals making it possible to load or unload either symbol or multiple symbols in a single clock cycle. Further, by partitioning the diagonal anti-diagonal structure, multiple respective symbols or plurality of symbols may be loaded or unloaded in a single clock cycle.

Abstract: In one embodiment, a computer-implemented method includes determining, by a processor, after the writing of data to a non-volatile memory block, one or more delta threshold voltage shift (TVS?) values configured to track temporary changes with respect to changes in the underlying threshold voltage distributions due to retention and/or read disturb errors. One or more overall threshold voltage shift values is calculated for the data written to the non-volatile memory block, the one or more overall threshold voltage shift values being a function of the one or more TVS? values to be used when writing data to the non-volatile memory block. The one or more overall threshold voltage shift values are stored.

Abstract: Methods and apparatus are provided for determining level-thresholds for q-level memory cells. A group of the memory cells are read to obtain respective read signal components. The read signal components are processed in dependence on signal level to produce a signal level vector, comprising a series of elements, indicative of the distribution of read signal components in order of signal level. A plurality of possible sets of q?1 elements corresponding, respectively, to q?1 level-thresholds which partition the signal level vector into q segments, is then defined. The q?1 level-thresholds for the group of memory cells are then determined by selecting from said possible sets that set for which a predetermined difference function, dependent on differences in signal level for elements in each of said q segments for the set, has an optimum value.

Abstract: Device for selecting a level for at least one read voltage for reading data stored in a multi-level memory device. The multi-level memory device includes a plurality of memory blocks, in which each of the memory blocks includes a plurality of word lines, each of the word lines being allocated to a plurality of memory pages and being indexed by a word line index. The device includes a first mapping unit for mapping each of the word line indices to one bin label, in which the number of bin labels is smaller than the number of word lines, and a second mapping unit for mapping each of the bin labels to a voltage information being indicative for at least one read voltage, in which the level for the at least one read voltage for reading data is selectable for each word line based on the respective word line index.

Abstract: In at least one embodiment, a controller of a non-volatile memory array retires physical pages within the non-volatile memory array on a page-by-page basis. The physical pages retired by the controller include a first physical page sharing a common set of memory cells with a second physical page. While the first physical page is retired, the controller retains the second physical page as an active physical page, writes dummy data to the first physical page, and writes data received from a host to the second physical page.

Abstract: A method, according to one embodiment, includes repeating the following sequence at least until a page stripe of a memory cache has at least a predetermined amount of data stored therein: receiving a compressed logical page of data, finding an open codeword having an amount of available space which is greater than or equal to a size of the compressed logical page, and storing the compressed logical page in the open codeword having the amount of available space which is greater than or equal to a size of the compressed logical page. The compressed logical page does not straddle out of the open codeword. Other systems, methods, and computer program products are described in additional embodiments.

Abstract: A repaired piston includes a crown composed of base and welding filler materials, and having an annular rim extending around a combustion bowl. A finite number of repaired defects are within the annular rim, and have a spatial distribution limited by a multidirectional spacing parameter, and a size distribution limited by a unidirectional sizing parameter.

Abstract: In a data storage system including a non-volatile memory array, a controller repeatedly determines at least one health metric of the non-volatile memory array during an operating lifetime of the non-volatile memory array. In response to determining the at least one health metric, the controller selectively varies an erase parameter of the non-volatile memory array over the operating lifetime of the non-volatile memory array, such that endurance of the non-volatile memory array is improved.

Abstract: In one embodiment, a computer-implemented method includes determining, by a processor, after the writing of data to a non-volatile memory block, one or more delta threshold voltage shift (TVS?) values configured to track temporary changes with respect to changes in the underlying threshold voltage distributions due to retention and/or read disturb errors. One or more overall threshold voltage shift values is calculated for the data written to the non-volatile memory block, the one or more overall threshold voltage shift values being a function of the one or more TVS? values to be used when writing data to the non-volatile memory block. The one or more overall threshold voltage shift values are stored.

Abstract: Methods and apparatus are provided for determining level-thresholds for q-level memory cells. A group of the memory cells are read to obtain respective read signal components. The read signal components are processed in dependence on signal level to produce a signal level vector, comprising a series of elements, indicative of the distribution of read signal components in order of signal level. A plurality of possible sets of q?1 elements corresponding, respectively, to q?1 level-thresholds which partition the signal level vector into q segments, is then defined. The q?1 level-thresholds for the group of memory cells are then determined by selecting from said possible sets that set for which a predetermined difference function, dependent on differences in signal level for elements in each of said q segments for the set, has an optimum value.

Abstract: Techniques for data deduplication in a data storage system include comparing a first attribute of a received data page to first attributes of one or more stored data pages. In response to the first attribute matching one of the first attributes, a second attribute of the received data page is compared to second attributes of the one or more data pages. In response to the second attribute of the received data page matching one of the second attributes, a fingerprint of the received data page is compared to fingerprints of the one or more data pages. In response to the fingerprint of the received data page matching one of the fingerprints, the received data page is discarded and replaced with a reference to the corresponding data page already stored in the storage system. In response to first attribute, the second attribute, or the fingerprint of the received data page not matching, the received data page is stored.

Abstract: A data storage system includes a controller and a non-volatile memory array having a plurality of blocks each including a plurality of physical pages. The controller maintains a logical-to-physical translation (LPT) data structure that maps logical addresses to physical addresses and implements a first data protection scheme that stripes write data over the plurality of physical blocks. In response to a read request requesting data from a target page stripe, the controller detecting errors in multiple physical pages of the target page stripe. In responsive to detecting errors in multiple physical pages of the target page stripe, the controller scans the LPT data structure to identify a set of logical addresses mapped to the target page stripe and triggers recovery of the target page stripe by a higher level controller that implements a second data protection scheme, wherein triggering recovery includes transmitting the set of logical addresses to the higher level controller.

Abstract: In at least one embodiment, a controller of a non-volatile memory array determines, for each of a plurality of regions of physical memory in the memory array, an associated health grade among a plurality of health grades and records the associated health grade. The controller also establishes a mapping between access heat and the plurality of health grades. In response to a write request specifying an address, the controller selects a region of physical memory to service the write request from a pool of available regions of physical memory based on an access heat of the address and the mapping and writes data specified by the write request to the selected region of physical memory.

Abstract: A set of K prefix codes for use in pseudo-dynamic compression are determined by seeding each of K clusters with a respective one of K data pages selected from a training data set, where K is a positive integer greater than 1. For each of the K randomly selected data pages, a prefix code is determined for its cluster utilizing Huffman encoding. Each remaining data page of the training data set is assigned to one of the K clusters whose prefix code yields the highest compression ratio. For each of the K clusters, the prefix code is updated by performing Lempel-Ziv (LZ) encoding on all pages assigned to that cluster, forming a sequence from results of the LZ encoding, and extracting an updated prefix code for the cluster from the sequence utilizing Huffman encoding. The set of K prefix codes determined for the K clusters is then output.

Abstract: In a data storage system including a non-volatile memory array, a controller determines a write frequency of a logical address mapped to a physical subset of the non-volatile memory array. Based on the determined write frequency of the logical address, the controller dynamically adjusts at least one operating parameter of a program/erase (P/E) cycle to optimize at least one of endurance of the block and data retention time of the physical subset of the non-volatile memory array. The at least one operating parameter includes one or more of a set including a pulse budget, a verify voltage and a verify threshold.