Abstract: The present invention refers to a method for writing data into a memory cell of a conductive bridging random access memory and to a memory circuit comprising memory cells with programmable metallization cells, particularly a CBRAM memory circuit. The embodiments of the prevent invention provide a method and a memory circuit for holding adjacently arranged bit lines at writing voltages during a writing operation of a selected memory cell to reduce voltage crosstalk.

Abstract: Memory reliability is improved by using redundancy to repair errors detected by ECC. In one embodiment, redundancy repairs errors which cannot be corrected by ECC. The redundancy can employ the use of electronic fuses, enabling repairs after an IC containing the memory is packaged. Redundancy can also be performed prior to packaging of the IC.

Abstract: A programming voltage is applied to source and drain in order to generate hot-hole injection at one end of the channel of a memory cell. The undesired programming of a neighboring memory cell is avoided by the application of an intermediate inhibit voltage to an adjacent bitline. This is done by precharging all the bitlines to the inhibit voltage, either by successively applying the inhibit voltage to every bitline individually or by applying both the upper and the lower programming voltage to one half of the bitlines and then short-circuiting all the bitlines to produce an intermediate voltage.

Abstract: Embodiments of the present invention provide methods and apparatuses for programming a programmable metallization cell (PMC) memory cell are provided. In one embodiment, a memory device includes a programmable metallization memory cell, a plate line connected to a first node of the memory cell, and a bitline connected to a second node of the memory cell. The memory device also includes circuitry configured to perform a write operation by applying a first voltage to the plate line and a second voltage to the bitline, perform an erase operation by applying the second voltage to the plate line and the first voltage to the bitline, and apply a voltage midway between the first voltage and the second voltage to the plate line when the write operation and the erase operation are not being performed.

Abstract: A programming voltage is applied to source and drain in order to generate hot-hole injection at one end of the channel of a memory cell. The undesired programming of a neighboring memory cell is avoided by the application of an intermediate inhibit voltage to an adjacent bitline. This is done by precharging all the bitlines to the inhibit voltage, either by successively applying the inhibit voltage to every bitline individually or by applying both the upper and the lower programming voltage to one half of the bitlines and then short-circuiting all the bitlines to produce an intermediate voltage.

Abstract: A semiconductor memory device has a particularly space-saving configuration of the memory areas and, in particular, of the selection devices assigned to the memory areas. During operation, each selection device can be assigned in a controllable manner to a plurality of memory areas such that selectively each of the selection devices can carry out an addressing and selection in one of the assigned memory areas.

Abstract: A semiconductor device includes an internal power supply, at least one semiconductor circuit block, a delay circuit, and a detecting circuit. The internal power supply outputs an initialization completion signal when initialized. The semiconductor circuit block operates on the basis of a voltage generated by the internal power supply. The delay circuit delays the initialization completion signal. The detecting circuit commands the semiconductor circuit block to start operations in response to the initialization completion signal delayed by the delay circuit and an externally input first input signal.

Abstract: The present invention relates to an electronic device comprising a memory cell with a resistive storage element having a first terminal and a second terminal. The resistive storage element can be switched between a first storage state with a first conductivity and a second storage state with a second conductivity. An access switch is coupled to the first terminal of the resistive storage element and to a node for connecting the first terminal of the resistive storage element to the node in an access state of the memory cell and for insulating the first terminal of the resistive storage element from the node in an idle state of the memory cell. A protecting switch is connected to the resistive storage element. The protecting switch, in the idle state of the memory cell, reduces the voltage across the resistive storage element produced by electromagnetic interference and, in the access state of the memory cell, enables the reading and the writing of the storage states of the resistive storage element.

Abstract: The present invention relates to a non-volatile memory cell for storage of a data item in an integrated circuit, comprising a resistive memory element which may have different conductance states depending on the stored data item, a memory unit for passing the stored data item to an integrated circuit, a read unit which can be activated in order to pass a data item on for storage in the memory unit as a function of the conductance state of the memory element, a control unit in order to activate the read unit so that the data item to be passed on is stored in the memory unit, and in order to deactivate the read unit after storage of the data item in the memory unit, such that the memory element is isolated from the memory unit.

Abstract: A dummy capacitor drive potential VDC is given to one electrode of a dummy capacitor, and a reference potential for determining a data value of a memory cell is generated in the other electrode thereof. A potential generator circuit for generating the potential VDC is composed of a BGR circuit outputting a potential VBGRTEMP having temperature dependency, and resistors R3 and R4, which are series-connected between an output terminal of the BGR circuit and a ground point. The potential VDC is output from a connection point of the resistors R3 and R4. Temperature dependency of the potential VDC is adjusted based on a resistance ratio of resistors R1-1, R1-2 and R2, and the absolute value is adjusted based on a resistance ratio of resistors R3 and R4.

Abstract: A method and apparatus for reading from a memory arrangement, in particular, for reading from a CBRAM or another memory arrangement based on resistively switching memory cells includes charging a bit line to a voltage value, discharging the bit line by a cell resistance, and subsequently assessing a resulting voltage difference in a measuring device, in particular, a differential sense amplifier.

Abstract: The invention relates to a memory component having memory cells based on an active solid electrolyte material which can be changed in terms of its resistance value. The active solid electrolyte material is embedded between a bottom and top electrode, can be switched between an on state with a low resistance and an off state with a high resistance by comparison therewith by application of a suitable electric field between said electrodes. A resistance material is embedded in parallel with the solid electrolyte material between the electrodes.

Abstract: A memory cell arrangement has a plurality of memory cells of the CBRAM type and a programming apparatus, the memory cells being arranged along bit lines and each bit line having a programming apparatus. The invention provides for the programming apparatus to comprise a charge storage device and a switchable charging apparatus. The inventive method for programming memory cells of the CBRAM type is carried out in such a manner that, a given quantity of an electrical charge is stored in a charge storage device, and the stored quantity of electrical charge is transferred to the memory cell to be programmed.

Abstract: Provided is a resistive memory arrangement having a cell array structured in rows and columns and having resistive memory cells connected to a drive element for driving. Each drive element is jointly connected to n cell resistors forming a memory cell, the cell resistors being CBRAM resistance elements, in particular, and also to a writing, reading and erasing method for a resistive memory arrangement realized with CBRAM resistance elements.

Abstract: In a memory circuit having memory cells which are connected in series between a ground line PL and a bit line BL and in each case have a resistance memory element said element having a bipolar switching behavior having an anode electrode and a cathode electrode, and a drive transistor connected in parallel with the resistance memory element, the drive transistors of the memory cells in each case are connected to a word line in order to switch the drive transistor on and off in such a way that a current path is formed via the associated drive transistor in a non-activated state of a memory cell and a current path is formed via the associated resistance memory element in an activated state of a memory cell, a first changeover switch being arranged at one end and a second changeover switch at other ends of the series of memory cells in order alternately to produce a connection between the series-connected memory cells and the ground line and the bit line in a manner dependent on an applied address.

Abstract: A dummy capacitor drive potential VDC is given to one electrode of a dummy capacitor, and a reference potential for determining a data value of a memory cell is generated in the other electrode thereof. A potential generator circuit for generating the potential VDC is composed of a BGR circuit outputting a potential VBGRTEMP having temperature dependency, and resistors R3 and R4, which are series-connected between an output terminal of the BGR circuit and a ground point. The potential VDC is output from a connection point of the resistors R3 and R4. Temperature dependency of the potential VDC is adjusted based on a resistance ratio of resistors R1-1, R1-2 and R2, and the absolute value is adjusted based on a resistance ratio of resistors R3 and R4.

Abstract: A switching device to be reversibly switched between an electrically isolating off-state and an electrically conducting on-state for use in, e.g., a reconfigurable interconnect. The device includes two separate electrodes, one of which being a reactive metal electrode and the other one being an inert electrode, and a solid state electrolyte arranged between the electrodes and being capable of electrically isolating the electrodes to define the off-state. The reactive metal electrode and the solid state electrolyte also being capable of forming a redox-system having a minimum voltage (turn-on voltage) to start a redox-reaction, which results in generating metal ions that are released into the solid state electrolyte. The metal ions are reduced to increase a metal concentration within the solid state electrolyte, wherein an increase of the metal concentration results in a conductive metallic connection bridging the electrodes to define the on-state.

Abstract: Improved sensing of ferroelectric memory cells is disclosed. When a memory access is initiated, the bitlines are precharged to a negative voltage, for example, ?0.5 to ?1.0V. This increases the effective plateline pulse (VPLH) to VPLH+the magnitude of the negative voltage. This results in an increase in the difference between VHI and VL0 read signals, thereby increasing the sensing window.

Abstract: A switching device to be reversibly switched between an electrically isolating off-state and an electrically conducting on-state for use in, e.g., a reconfigurable interconnect. The device includes two separate electrodes, one of which being a reactive metal electrode and the other one being an inert electrode, and a solid state electrolyte arranged between the electrodes and being capable of electrically isolating the electrodes to define the off-state. The reactive metal electrode and the solid state electrolyte also being capable of forming a redox-system having a minimum voltage (turn-on voltage) to start a redox-reaction, which results in generating metal ions that are released into the solid state electrolyte. The metal ions are reduced to increase a metal concentration within the solid state electrolyte, wherein an increase of the metal concentration results in a conductive metallic connection bridging the electrodes to define the on-state.

Abstract: The present invention relates to a switching device to be irreversibly switched from an electrically isolating off-state into an electrically conducting on-state for use in a configurable interconnect, comprising two separate electrodes, at least one of which being a reactive metal electrode, and a solid state electrolyte arranged between said electrodes and being capable of electrolyte isolating said electrodes to define said off-state, said electrodes and said solid state electrolyte forming a redox-system having a mini-mum voltage (“turn-on voltage”) to start a redox reaction, the redox reaction resulting in the generation of metal ions to be released into said solid state electrolyte, the metal ions being reduced to increase a metal concentration within said solid state electrolyte, wherein an increase of said metal concentration results in a conductive metallic connection bridging the electrodes to define the on-state.