Abstract: A ferroelectric memory array includes a plurality of memory pages each formed of a plurality of ferroelectric memory cells. The ferroelectric memory cells are supplied by common word lines. Status memory cells are connected to each of the plurality of memory pages, each status memory cell stores the status of the memory page to which it is connected. A plurality of sense amplifiers each receives inputs from a pair of bit lines. Each of the bit lines receives inputs from the ferroelectric memory cells of a plurality of the memory pages. The sense amplifiers write back data into the memory cells and status cells in reversed states following read operations.

Abstract: A method for reducing noise coupling in a memory array is disclosed. The memory array includes a plurality memory cells interconnected by wordlines, bitlines, and platelines. The memory cells are arranged in columns having first and second bitlines coupled to a sense amplifier. During a memory access, at least adjacent bitlines pairs are not activated. The selected bitline pair or pairs are provided with a plateline pulse.

Abstract: A ferroelectric memory array includes a plurality of memory pages each formed of a plurality of ferroelectric memory cells. The ferroelectric memory cells are supplied by common word lines. Status memory cells are connected to each of the plurality of memory pages, each status memory cell stores the status of the memory page to which it is connected. A plurality of sense amplifiers each receives inputs from a pair of bit lines. Each of the bit lines receives inputs from the ferroelectric memory cells of a plurality of the memory pages. The sense amplifiers write back data into the memory cells and status cells in reversed states following read operations.

Abstract: A semiconductor component having a material-reinforced contact area formed of a metal layer is disclosed. The contact area is jointly formed by a second metal area of a first metal layer and a fourth metal area of a second metal layer which is to be contacted. A thickness of the contact area material is at least twice that of a single metal layer and thereby prevents penetrative etching when a hole is created for contacting the metal layer.

Abstract: A redundancy unit includes first and second fuse blocks for programming the redundancy element. One fuse block has laser blowable fuses and the other electrical fuses. The redundancy unit can be programmed by either one of the fuse blocks, enabling the redundancy unit to able to be used for defects identified before packaging and as well as after.

Abstract: A memory IC having improved sensing during reads is disclosed. The IC includes the use of first and second reference voltages for sensing to compensate for asymmetry that exists between cells on bitline true and bitline complement. The first reference voltage is used for sensing a cell on bitline true while the second reference voltage is used for sensing a cell on bitline complement.

Abstract: A test circuit for testing differential read signals during a memory access is disclosed. The test circuit is coupled to a pair of bit lines. During a read access, a selected memory cell produces a differential read signal on the bit lines. When the test circuit is activated, the magnitude of the differential read signal is varied. This enables easy testing of read signal margins in, for example, memory ICs.

Abstract: The present invention provides a semiconductor memory test mode configuration. A first capacitor stores digital data and connects a cell plate line to a first bit-line through a first select transistor. The first select transistor is activated through a connection to a word line. At least one reference capacitor provides a reference voltage to a reference bit-line. A sense amplifier is connected to the first and reference bit-lines and measures a differential read signal on the first and reference bit-lines. A charge path reduces the differential read signal to determine the signal margin of the semiconductor memory.

Abstract: A data storage device comprises a controller, a FeRAM memory unit, and a flash memory unit having a much higher data storage capacity than the FeRAM memory unit. Initially, when data is received by the data storage device, the controller stores it in the FeRAM memory unit. This can be done very quickly, since FeRAM devices have a high write rate. Subsequently, the controller transfers the data to the flash memory unit. Thus, the data storage device combines the high storage rate ability of FeRAM devices and the high storage capacity of flash memory devices.

Abstract: An improved redundancy scheme for chained memory architecture is disclosed. The redundancy scheme comprises including redundant cells as part of the memory chain. As such, a redundant cell is used to repair a defective cell within the chain. This eliminates the need in conventional chained architecture to replace the whole memory block when there is a defective cell.

Abstract: A semiconductor memory test mode configuration includes a first capacitor for storing digital data. The first capacitor connects a cell plate line to a first bit line through a first select transistor which is activated through a connection to a word line. A second capacitor for storing digital data connects the cell plate line to a second bit line through a second select transistor which is also activated through a connection to the word line. A sense amplifier is connected to the first and second bit lines for measuring a differential read signal on the first and second bit lines. A constant current mover, for example a constant current sink or source, is connected to the first bit line through a third transistor for changing the amount of charge on the first bit line when the third transistor is turned on to reduce the differential read signal.

Abstract: A memory matrix has at least one cell array including column lines and row lines. Memory elements are situated at points where the row lines and column lines intersect one another. In each case two adjacent lines are guided such that they cross one another in such a way that the two lines change their spatial configurations in sections along the direction in which they run. Thus an overcoupling of signals between the lines is minimized.

Abstract: The invention relates to an MRAM configuration that includes a selection transistor connected to several MTJ memory cells. The selection transistor has an increased channel width.

Abstract: An MRAM configuration has selection transistors and MTJ layer sequences lying in parallel with each other in a memory cell matrix. A considerable space saving can thus be achieved and therefore the MRAM configuration is less expensive to manufacture and has a greater packing density. In addition, the MRAM configuration allows a rapid read access with a minimal area requirement.

Abstract: An integrated magnetoresistive semiconductor memory system, in which n memory cells that contain two magnetic layers each separated by a thin dielectric barrier, and associated word lines and bit lines that cross one another are vertically stacked in n layers. The system further contains a decoding circuit for selecting one of the n memory layers. The decoding circuit, on both ends of a word line or a bit line, is provided with one configuration each that contains n layer selecting transistors for selecting one of the n memory layers, and with a line selection transistor for selecting the respective horizontal word line or bit line on which a voltage is to be impressed.

Abstract: A semiconductor device includes an internal power supply, at least one semiconductor circuit block, a delay circuit, and a detecting circuit. The internal power supply outputs an initialization completion signal when initialized. The semiconductor circuit block operates on the basis of a voltage generated by the internal power supply. The delay circuit delays the initialization completion signal. The detecting circuit commands the semiconductor circuit block to start operations in response to the initialization completion signal delayed by the delay circuit and an externally input first input signal.

Abstract: A method for reducing noise coupling in a memory array is disclosed. The memory array includes a plurality memory cells interconnected by wordlines, bitlines, and platelines. The memory cells are arranged in columns having first and second bitlines coupled to a sense amplifier. During a memory access, at least adjacent bitlines pairs are not activated. The selected bitline pair or pairs are provided with a plateline pulse.

Abstract: An improved architecture which reduces the adverse impact of the disturb pulse on non-selected ferroelectric memory cells is disclosed. The architecture provides plateline selection switches for selectively coupling memory groups on the selected side of the memory block to the plateline and decoupling the non-selected side of the memory block from the plateline. By decoupling the non-selected side of the memory block from the plateline, the plate pulse does not adversely affect the memory cells in the non-selected side of the memory block.

Abstract: The present invention provides a test mode section for facilitating a worst case product test sequence for signal margin to ensure full product functionality over the entire component lifetime taking all aging effects into account. A semiconductor memory test mode configuration includes a first capacitor for storing digital data The capacitor connects a cell plate line to a first bit line through a first select transistor. The first select transistor is activated through a connection to a word line. A second capacitor stores digital data and connects the cell plate line to a second bit line through a second select transistor. The second select transistor is also activated through a connection to the word line. A sense amplifier is connected to the first and second bit lines and measures a differential read signal on the first and second bit lines.

Abstract: The present invention provides a test mode section for facilitating a worst case product test sequence for signal margin to ensure full product functionality over the entire component lifetime taking all aging effects into account. A semiconductor memory test mode configuration includes a first capacitor for storing digital data. The first capacitor connects a cell plate line to a first bit line through a first select transistor. The first select transistor is activated through a connection to a word line. A second capacitor for storing digital data connects the cell plate line to a second bit line through a second select transistor. The second select transistor is also activated through a connection to the word line. A sense amplifier is connected to the first and second bit lines for measuring a differential read signal on the first and second bit lines.