Patents by Inventor Thomas V. Sikina

Thomas V. Sikina has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11317502
    Abstract: Methods and apparatus for providing a cavity defined by conductive walls, a printed circuit board (PCB) within the cavity, and shorting posts extending into the cavity to suppress higher order modes generated by operation of the PCB.
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: April 26, 2022
    Assignee: Raytheon Company
    Inventors: Thomas V. Sikina, John P. Haven, James E. Benedict, William J. Clark, Channing P. Favreau, Erika Klek, Mikhail Pevzner, Donald G. Hersey, Gregory G. Beninati, Thomas J. Tellinghuisen
  • Patent number: 11289814
    Abstract: The concepts, systems, circuits and techniques described herein are directed toward a spiral antenna which may be provided using additive manufacturing technology so as to provide an antenna capable of operation at frequencies which are higher than spiral antennas manufactured using standard photo-etch or printed circuit board (PCB) manufacturing processes.
    Type: Grant
    Filed: November 5, 2018
    Date of Patent: March 29, 2022
    Assignee: RAYTHEON COMPANY
    Inventors: Peter J. Adams, Thomas V. Sikina, John P. Haven, James E. Benedict
  • Publication number: 20220052460
    Abstract: A low profile array (LPA) includes an antenna element array layer having at least one Faraday wall, and a beamformer circuit layer coupled to the antenna element array layer. The beamformer circuit layer has at least one Faraday wall. The Faraday walls extends between ground planes associated with at least one of the antenna element array layer and the beamformer circuit layer.
    Type: Application
    Filed: October 26, 2021
    Publication date: February 17, 2022
    Inventors: Thomas V. Sikina, John P. Haven, James E. Benedict, Jonathan E. Nufio-Molina, Andrew R. Southworth
  • Publication number: 20210400820
    Abstract: A process of fabricating a circuit includes providing a first sheet of dielectric material including a first top surface having at least one first conductive trace and a second sheet of dielectric material including a second top surface having at least one second conductive trace, depositing a first solder bump on the at least one first conductive trace, applying the second sheet of dielectric material to the first sheet of dielectric material with bonding film sandwiched in between, bonding the first and second sheets of dielectric material to one another, and providing a conductive material to connect the first solder bump on the at least one first conductive trace to the at least one second conductive trace.
    Type: Application
    Filed: September 2, 2021
    Publication date: December 23, 2021
    Inventors: James E. Benedict, Gregory G. Beninati, Mikhail Pevzner, Thomas V. Sikina, Andrew R. Southworth
  • Publication number: 20210368629
    Abstract: An apparatus for automating the fabrication of a copper vertical launch (CVL) within a printed circuit board (PCB) includes a feed mechanism to feed and extrude copper wire from a spool of copper wire and a wire cutting and gripping mechanism to receive copper wire from the feed mechanism, cut and secure a segment of copper wire, insert the segment of copper wire into a hole formed within the PCB, solder an end of the segment of copper wire to a signal trace of the PCB, and flush cut an opposite end of the segment of the copper wire to a surface of the PCB. The wire cutting and gripping mechanism includes a wire cutter to flush cut the segment of copper wire and an integrated heated gripper device to receive the copper wire from the spool of copper wire and cut and grab a segment from copper wire.
    Type: Application
    Filed: August 6, 2021
    Publication date: November 25, 2021
    Inventors: Mikhail Pevzner, James E. Benedict, Andrew R. Southworth, Thomas V. Sikina, Kevin Wilder, Matthew Souza, Aaron Michael Torberg
  • Publication number: 20210360772
    Abstract: Methods and apparatus for providing a cavity defined by conductive walls, a printed circuit board (PCB) within the cavity, and shorting posts extending into the cavity to suppress higher order modes generated by operation of the PCB.
    Type: Application
    Filed: May 15, 2020
    Publication date: November 18, 2021
    Applicant: Raytheon Company
    Inventors: Thomas V. Sikina, John P. Haven, James E. Benedict, William J. Clark, Channing P. Favreau, Erika Klek, Mikhail Pevzner, Donald G. Hersey, Gregory G. Beninati, Thomas J. Tellinghuisen
  • Publication number: 20210359429
    Abstract: Methods and apparatus for providing a radiator having an antenna comprising a patch antenna layer and a first ground plane layer, wherein the antenna has a reactive field region of the radiator between the patch antenna layer and the first ground plane layer, and an integrated circuit located in the active region.
    Type: Application
    Filed: May 15, 2020
    Publication date: November 18, 2021
    Applicant: Raytheon Company
    Inventors: Thomas V. Sikina, John P. Haven, Channing P. Favreau
  • Patent number: 11171101
    Abstract: A process of fabricating an electromagnetic circuit includes providing a first sheet of dielectric material including a top surface having at least one conductive trace and depositing a solder bump on the at least one conductive trace. The process further includes applying a second sheet of dielectric material to the first sheet of dielectric material with bond film sandwiched in between, the second sheet of dielectric material having a through-hole providing access to the solder bump. The process further includes bonding the first and second dielectric materials to one another and removing bond film resin from the solder bump. The process further includes machining the solder bump by the drilling or milling process to achieve a desired amount of solder in the solder bump.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: November 9, 2021
    Assignee: RAYTHEON COMPANY
    Inventors: James E. Benedict, Paul A. Danello, Mikhail Pevzner, Thomas V. Sikina, Andrew R. Southworth
  • Publication number: 20210337651
    Abstract: A circuit assembly is provided and includes a printed circuit board (PCB) having a circuit element region and defining a trench surrounding an entirety of the circuit element region, a circuit element disposed within the circuit element region of the PCB; and a Faraday wall. The Faraday wall includes a solid, unitary body having a same shape as the trench. The Faraday wall is disposed within the trench to surround an entirety of the circuit element.
    Type: Application
    Filed: July 2, 2021
    Publication date: October 28, 2021
    Inventors: Andrew Southworth, Kevin Wilder, James Benedict, Mary K. Herndon, Thomas V. Sikina, John P. Haven
  • Patent number: 11158955
    Abstract: A low profile array (LPA) includes an antenna element array layer having at least one Faraday wall, and a beamformer circuit layer coupled to the antenna element array layer. The beamformer circuit layer has at least one Faraday wall. The Faraday walls extends between ground planes associated with at least one of the antenna element array layer and the beamformer circuit layer.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: October 26, 2021
    Assignee: RAYTHEON COMPANY
    Inventors: Thomas V. Sikina, John P. Haven, James E. Benedict, Jonathan E. Nufio-Molina, Andrew R. Southworth
  • Patent number: 11145977
    Abstract: An array includes a support structure configured to support columns of beamformer assemblies, and a plurality of beamformer assemblies supported by the support structure. Each beamformer assembly includes at least one beamformer having at least one first beamformer segment and at least one second beamformer segment configured to interconnect with the first beamformer segment.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: October 12, 2021
    Assignee: RAYTHEON COMPANY
    Inventors: Kevin Wilder, Jonathan E. Nufio-Molina, Phillip W. Thiessen, Thomas V. Sikina, James E. Benedict, Andrew R. Southworth, Erika Klek
  • Patent number: 11145952
    Abstract: A communications array includes a support structure configured to array elements, and a plurality of array elements supported by the support structure. Each array element is fabricated from an advanced manufacturing techniques (AMT) process. The support structure may be fabricated from a printed circuit board (PCB) or similar dielectric material. Each array element may include a radiator and/or a beamformer manufactured using the AMT process. The communications array further may include a copper vertical launch (CVL) and/or an electromagnetic boundary.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: October 12, 2021
    Assignee: RAYTHEON COMPANY
    Inventors: Thomas V. Sikina, John P. Haven, Kevin Wilder, James E. Benedict, Andrew R. Southworth, Mary K. Herndon
  • Publication number: 20210305187
    Abstract: A process of fabricating an electromagnetic circuit includes providing a first sheet of dielectric material including a top surface having at least one conductive trace and depositing a solder bump on the at least one conductive trace. The process further includes applying a second sheet of dielectric material to the first sheet of dielectric material with bond film sandwiched in between, the second sheet of dielectric material having a through-hole providing access to the solder bump. The process further includes bonding the first and second dielectric materials to one another and removing bond film resin from the solder bump. The process further includes machining the solder bump by the drilling or milling process to achieve a desired amount of solder in the solder bump.
    Type: Application
    Filed: March 31, 2020
    Publication date: September 30, 2021
    Inventors: James E. Benedict, Paul A. Danello, Mikhail Pevzner, Thomas V. Sikina, Andrew R. Southworth
  • Publication number: 20210296751
    Abstract: A RAMP-radio frequency (RAMP-RF) assembly is provided and includes an RF panel including a microstrip interface, a plate including a stripline interface and a microstrip-to-stripline transition element operably connectable to the microstrip interface and to the stripline interface.
    Type: Application
    Filed: March 18, 2020
    Publication date: September 23, 2021
    Inventors: JAMES BENEDICT, Erika Klek, John P. Haven, Michael Souliotis, Thomas V. Sikina, Andrew R. Southworth, Kevin Wilder
  • Patent number: 11122692
    Abstract: A process of fabricating a circuit includes providing a first sheet of dielectric material including a first top surface having at least one first conductive trace and a second sheet of dielectric material including a second top surface having at least one second conductive trace, depositing a first solder bump on the at least one first conductive trace, applying the second sheet of dielectric material to the first sheet of dielectric material with bonding film sandwiched in between, bonding the first and second sheets of dielectric material to one another, and providing a conductive material to connect the first solder bump on the at least one first conductive trace to the at least one second conductive trace.
    Type: Grant
    Filed: June 11, 2020
    Date of Patent: September 14, 2021
    Assignee: RAYTHEON COMPANY
    Inventors: James E. Benedict, Gregory G. Beninati, Mikhail Pevzner, Thomas V. Sikina, Andrew R. Southworth
  • Patent number: 11121474
    Abstract: Described herein is a low profile radiator (LPR) manufactured using additive manufacturing technology (AMT). Such an AMT radiator is suitable for use in an array antenna which may be fabricated using AMT manufacturing processes.
    Type: Grant
    Filed: November 5, 2018
    Date of Patent: September 14, 2021
    Assignee: RAYTHEON COMPANY
    Inventors: John P. Haven, Thomas V. Sikina, Peter J. Adams, James E. Benedict
  • Patent number: 11109489
    Abstract: An apparatus for automating the fabrication of a copper vertical launch (CVL) within a printed circuit board (PCB) includes a feed mechanism to feed and extrude copper wire from a spool of copper wire and a wire cutting and gripping mechanism to receive copper wire from the feed mechanism, cut and secure a segment of copper wire, insert the segment of copper wire into a hole formed within the PCB, solder an end of the segment of copper wire to a signal trace of the PCB, and flush cut an opposite end of the segment of the copper wire to a surface of the PCB. The wire cutting and gripping mechanism includes a wire cutter to flush cut the segment of copper wire and an integrated heated gripper device to receive the copper wire from the spool of copper wire and cut and grab a segment from copper wire.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: August 31, 2021
    Assignee: RAYTHEON COMPANY
    Inventors: Mikhail Pevzner, James E. Benedict, Andrew R. Southworth, Thomas V. Sikina, Kevin Wilder, Matthew Souza, Aaron Michael Torberg
  • Patent number: 11107610
    Abstract: A method includes blending a dielectric material including a titanate with a carbon-based ink to form a modified carbon-based ink. The method also includes printing the modified carbon-based ink onto a structure. The method further includes curing the printed modified carbon-based ink on the structure at a temperature that does not exceed about 250° C. In addition, the method includes processing the cured printed modified carbon-based ink to form a thick film resistor. Blending the dielectric material with the carbon-based ink causes the modified carbon-based ink to have a resistivity that is at least double a resistivity of the carbon-based ink.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: August 31, 2021
    Assignees: Raytheon Company, University of Massachusetts
    Inventors: Erika C. Klek, Mary K. Herndon, Thomas V. Sikina, James E. Benedict, Andrew R. Southworth, Kevin M. Wilder, Oshadha K. Ranasingha, Alkim Akyurtlu
  • Publication number: 20210249771
    Abstract: A dual band frequency selective radiator array includes a high band radiator array disposed on a dielectric layer for transmitting and receiving high band radar signals; a low band radiator array disposed on a front side of the high band radiator array for transmitting and receiving low band radar signals; a frequency selective surface (FSS) tuned to the high band radar signals forming a surface of the low band radiator array and passes the high band radar signals to the high band radiator array; and a single aperture disposed in front of the low band radiator array, the high band radiator array and the FSS for both the low band radiator array and the high band radiator array for transmitting and receiving the radar signals.
    Type: Application
    Filed: February 10, 2020
    Publication date: August 12, 2021
    Inventors: Jack J. Schuss, Phillip W. Thiessen, Thomas V. Sikina
  • Publication number: 20210249787
    Abstract: A dual band dipole radiator array includes a high band radiator array disposed on a dielectric layer for transmitting and receiving high band radar signals; a low band radiator array disposed on a front side of the high band radiator array for transmitting and receiving low band radar signals; a foam material between the low band radiator array and the high band radiator array for support; and a single aperture for both the low band radiator array and the high band radiator array for transmitting and receiving the radar signals, where the low band radiator array is comprised of a plurality of dipole structures disposed within the foam material and tuned to pass through high band radar signals to or from the high band radiator array.
    Type: Application
    Filed: February 10, 2020
    Publication date: August 12, 2021
    Inventors: Jack J. Schuss, Phillip W. Thiessen, Thomas V. Sikina