Patents by Inventor Ti Wang

Ti Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200105557
    Abstract: A wafer processing tool is capable of detecting wafer warpage. The wafer processing tool includes a wafer holder on which a wafer is held and at least one sensor set. The at least one sensor set is disposed above the wafer or under the wafer, and a projection of each of the at least one sensor set on the wafer radially extending from a center of the wafer to an edge of the wafer. The at least one sensor set is configured to scan an entire surface of the wafer so as to measure warpage of the wafer while the wafer holder and the at least one sensor set are rotatable relative to each other.
    Type: Application
    Filed: December 12, 2018
    Publication date: April 2, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chao-Hsiung YEH, Hsuan CHANG, Jen-Ti WANG, Chin-Tsan CHEN, Kuo-Fong CHUANG
  • Publication number: 20200075378
    Abstract: A method for storage a workpiece used in fabrication of a semiconductor device includes disposing the workpiece on a workpiece carrier, disposing the workpiece carrier with the workpiece in a workpiece container via a workpiece storage system, identifying a content of the workpiece container, and adjusting a storage condition inside the workpiece container in response to the content of the workpiece container via the workpiece storage system.
    Type: Application
    Filed: July 24, 2019
    Publication date: March 5, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tzu-Chi CHIU, Jen-Ti WANG, Ting-Wei WANG, Kuo-Fong CHUANG
  • Publication number: 20200062285
    Abstract: A monitor vehicle for a rail system includes a wheeled trolley, an overhead vehicle, a supporting structure, and a first sensor. The wheeled trolley is above a rail of the rail system, is operable to move over the rail, and has a bottom surface. The overhead vehicle body is suspended by the wheeled trolley and below the rail. The supporting structure connects the wheeled trolley and the overhead vehicle body. The first sensor is on the bottom surface of the wheeled trolley and is configured to detect a first parameter of the rail of the rail system.
    Type: Application
    Filed: November 4, 2019
    Publication date: February 27, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Hung CHIEN, Jen-Ti WANG, Fu-Hsien LI, Chih-Hung LIU, Yung-Lin HSU
  • Publication number: 20190371636
    Abstract: A fault detection method in a semiconductor fabricating factory is provided. The method includes delivering a test vehicle along a rail to a test region. The method further includes projecting a test signal from a transducer that is positioned on the test vehicle over a check board when the test vehicle is located within the test region. The check board and the test vehicle are arranged along an axis that is parallel to the rail. The method also includes performing an analysis of the test signal projected over the check board. In addition, the method includes issuing a warning alarm when an abnormality is detected based on the analysis result.
    Type: Application
    Filed: May 29, 2018
    Publication date: December 5, 2019
    Inventors: Chun-Jung HUANG, Yung-Lin HSU, Kuang-Huan HSU, Wei-Chih CHEN, Jen-Ti WANG, Chih-Hung LIU
  • Patent number: 10464583
    Abstract: A monitor vehicle for a rail system includes a wheeled trolley, an overhead vehicle body, at least one supporting structure, and at least one first sensor. The wheeled trolley is operable to move over one or more rails of the rail system. The supporting structure connects the wheeled trolley and overhead vehicle body. The first sensor is on the wheeled trolley and configured to detect at least one first parameter of the one or more rails of the rail system.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: November 5, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Hung Chien, Jen-Ti Wang, Fu-Hsien Li, Chih-Hung Liu, Yung-Lin Hsu
  • Publication number: 20190131119
    Abstract: A method includes receiving a carrier with a plurality of wafers inside; supplying a purge gas to an inlet of the carrier; extracting an exhaust gas from an outlet of the carrier; and generating a health indicator of the carrier while performing the supplying of the purge gas and the extracting of the exhaust gas.
    Type: Application
    Filed: October 26, 2017
    Publication date: May 2, 2019
    Inventors: Jen-Ti Wang, Chih-Wei Lin, Fu-Hsien Li, Yi-Ming Chen, Cheng-Ho Hung
  • Patent number: 10161033
    Abstract: A cleaning module adapted for cleaning a load port of a processing apparatus in semiconductor fabrication is provided. The cleaning module includes a housing having at least one opening formed on a bottom wall panel of the housing. The cleaning module further includes a filter unit positioned in the housing. The leaning module also includes a driving assembly. The driving assembly is arranged to correspond to the opening and positioned in the housing. The driving assembly is used to create an air flow from outside of the housing via the opening to the filter unit. The filter unit is used to separate particles or contaminants from the air flow.
    Type: Grant
    Filed: August 21, 2015
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsueh-Lei Wang, Jen-Ti Wang, Ting-Wei Wang, Wen-Chieh Tsou
  • Publication number: 20180148076
    Abstract: A monitor vehicle for a rail system includes a wheeled trolley, an overhead vehicle body, at least one supporting structure, and at least one first sensor. The wheeled trolley is operable to move over one or more rails of the rail system. The supporting structure connects the wheeled trolley and overhead vehicle body. The first sensor is on the wheeled trolley and configured to detect at least one first parameter of the one or more rails of the rail system.
    Type: Application
    Filed: July 10, 2017
    Publication date: May 31, 2018
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Hung CHIEN, Jen-Ti WANG, Fu-Hsien LI, Chih-Hung LIU, Yung-Lin HSU
  • Patent number: 9978745
    Abstract: A bipolar junction transistor (BJT) includes a semiconductor substrate and a first isolation structure. The semiconductor substrate includes a first fin structure disposed in an emitter region, a second fin structure disposed in a base region, and a third fin structure disposed in a collector region. The first, the second, and the third fin structures are elongated in a first direction respectively. The base region is adjacent to the emitter region, and the base region is located between the emitter region and the collector region. The first isolation structure is disposed between the first fin structure and the second fin structure, and a length of the first isolation structure in the first direction is shorter than or equal to 40 nanometers. An effective base width of the BJT may be reduced by the disposition of the first isolation structure, and a current gain of the BJT may be enhanced accordingly.
    Type: Grant
    Filed: October 11, 2016
    Date of Patent: May 22, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kuan-Ti Wang, Ling-Chun Chou, Kun-Hsien Lee
  • Publication number: 20180118398
    Abstract: An automated method of unpacking a container containing semiconductor wafers from a sealed bag is provided. The method includes inflating the bag with a gas using an automated gas dispenser. After inflating the bag, the bag is cut using an automated cutting device to expose the container, and the cut bag is removed from around the container.
    Type: Application
    Filed: October 31, 2016
    Publication date: May 3, 2018
    Inventors: Fu-Hsien LI, Chi-Feng TUNG, Chi Yuan CHU, Jen-Ti WANG, Hsiang Yin SHEN
  • Publication number: 20180068998
    Abstract: A bipolar junction transistor (BJT) includes a semiconductor substrate and a first isolation structure. The semiconductor substrate includes a first fin structure disposed in an emitter region, a second fin structure disposed in a base region, and a third fin structure disposed in a collector region. The first, the second, and the third fin structures are elongated in a first direction respectively. The base region is adjacent to the emitter region, and the base region is located between the emitter region and the collector region. The first isolation structure is disposed between the first fin structure and the second fin structure, and a length of the first isolation structure in the first direction is shorter than or equal to 40 nanometers. An effective base width of the BJT may be reduced by the disposition of the first isolation structure, and a current gain of the BJT may be enhanced accordingly.
    Type: Application
    Filed: October 11, 2016
    Publication date: March 8, 2018
    Inventors: Kuan-Ti Wang, Ling-Chun Chou, Kun-Hsien Lee
  • Publication number: 20180024513
    Abstract: In a data management system, a host is configured to send a data access request to a target measurement device among a plurality of measurement devices using a USB dongle. When the USB dongle is unable to receive data from the target measurement device within a predetermined period of time, the host determines that a connection interruption has occurred and releases the connection resource of the USB dongle.
    Type: Application
    Filed: June 21, 2017
    Publication date: January 25, 2018
    Inventors: Hao-Chun Tung, Chen-Chen Tsai, Chien-Sen Weng, Yung-Ti Wang
  • Patent number: 9853021
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a first fin-shaped structure on a substrate; forming a shallow trench isolation (STI) adjacent to the first fin-shaped structure; and forming a gate structure on the first fin-shaped structure and the STI. Preferably, the gate structure comprises a left portion and the right portion and the work functions in the left portion and the right portion are different.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: December 26, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kuan-Ti Wang, Ling-Chun Chou, Kun-Hsien Lee
  • Publication number: 20170049284
    Abstract: A cleaning module adapted for cleaning a load port of a processing apparatus in semiconductor fabrication is provided. The cleaning module includes a housing having at least one opening formed on a bottom wall panel of the housing. The cleaning module further includes a filter unit positioned in the housing. The leaning module also includes a driving assembly. The driving assembly is arranged to correspond to the opening and positioned in the housing. The driving assembly is used to create an air flow from outside of the housing via the opening to the filter unit. The filter unit is used to separate particles or contaminants from the air flow.
    Type: Application
    Filed: August 21, 2015
    Publication date: February 23, 2017
    Inventors: Hsueh-Lei WANG, Jen-Ti WANG, Ting-Wei WANG, Wen-Chieh TSOU
  • Publication number: 20150323830
    Abstract: A display panel and a method for cutting the same are disclosed. The display panel of the present invention comprises: a first substrate comprising at least a first side, a first edge, and a turning edge connecting the first side and the first edge, wherein the turning edge has a curve shape; and a second substrate disposed opposite to the first substrate and comprising at least a second edge partially overlapped with the first edge, wherein the second substrate is protruded from the turning edge at a region near to the turning edge of the first substrate, wherein a virtual extension line of the first side and the second edge intersect at an intersection point, and a minimum distance between the intersection point and the turning edge is in a range from 0.1 mm to 2.1 mm.
    Type: Application
    Filed: April 3, 2015
    Publication date: November 12, 2015
    Inventors: Huan-Kaung PENG, Wei-Ti WANG, Hsin-Hsu SHEN, Yan-Li WANG, Wei ZHANG, Shih-Hsiung WU
  • Patent number: 8022206
    Abstract: Furo[3,2-c]Pyridine and Thieno[3,2-c]pyridine compounds of Formula I, and pharmaceutically acceptable salts thereof, preparation, intermediates, pharmaceutical compositions, and use, such as in disease treatment, including cancers, including conditions in which EMT is involved, including conditions mediated by protein kinase activity such as RON and/or MET.
    Type: Grant
    Filed: February 6, 2009
    Date of Patent: September 20, 2011
    Assignee: OSI Pharmaceuticals, LLC
    Inventors: An-Hu Li, Arno G. Steinig, Andrew Kleinberg, Qinghua Weng, Mark J. Mulvihill, Jing Wang, Xin Chen, Ti Wang, Hanqing Dong, Meizhong Jin
  • Patent number: 7593264
    Abstract: Embodiments of addressing the programming disturb effect are shown. A medium voltage having a magnitude between the programming voltage and ground is applied to a metal bit line among the cells that are subject to the program disturb effect.
    Type: Grant
    Filed: September 14, 2006
    Date of Patent: September 22, 2009
    Assignee: Macronix International Co., Ltd.
    Inventors: Yi Te Shih, Jer-Hao Hsu, Yi-Ti Wang, Hsueh-Yi Lee
  • Publication number: 20090197864
    Abstract: Furo[3,2-c]Pyridine and Thieno[3,2-c]pyridine compounds of Formula I, and pharmaceutically acceptable salts thereof, preparation, intermediates, pharmaceutical compositions, and use, such as in disease treatment, including cancers, including conditions in which EMT is involved, including conditions mediated by protein kinase activity such as RON and/or MET.
    Type: Application
    Filed: February 6, 2009
    Publication date: August 6, 2009
    Inventors: An-Hu Li, Arno G. Steinig, Andrew Kleinberg, Qinghua Weng, Mark J. Mulvihill, Jing Wang, Xin Chen, Ti Wang, Hanqing Dong, Meizhong Jin
  • Patent number: 7323926
    Abstract: A charge pump circuit comprises a first pump stage, including a first sub-pump coupled to a first pre-charge MOSFET transistor, wherein the first sub-pump is used to pump down a gate of the first pre-charge MOSFET transistor to thereby increase the pre-charge efficiency of the first pre-charge MOSFET transistor. The higher efficiency the pre-charge MOSFET is, the lower the gate level of a pass transistor is. Thus, the charge sharing efficiency becomes better, and the body effect will be eliminated. The following pump stage is the same as the first pump stage. In addition, this pre-charging is implemented by PMOSFET only; therefore, only a single well is needed and then a small layout area can be achieved. Consequently, a high efficiency negative pump can be obtained.
    Type: Grant
    Filed: December 21, 2004
    Date of Patent: January 29, 2008
    Assignee: Macronix International Co., Ltd.
    Inventors: Kuan-Yeu Chen, Yi-Ti Wang
  • Publication number: 20070159887
    Abstract: Embodiments of addressing the programming disturb effect are shown. A medium voltage having a magnitude between the programming voltage and ground is applied to a metal bit line among the cells that are subject to the program disturb effect.
    Type: Application
    Filed: September 14, 2006
    Publication date: July 12, 2007
    Applicant: Macronix International Co., Ltd.
    Inventors: Yi Te Shih, Jer Hao Hsu, Yi-Ti Wang, Hsueh-Yi Lee