Abstract: A charge pump voltage regulator is provided. The charge pump voltage regulator includes a charge pump circuit, where an output terminal of the charge pump circuit outputs a stable voltage. The charge pump voltage regulator also includes a voltage divider circuit suitable to divide the stable voltage to output a divided voltage and a clock oscillator providing a drive clock signal for the charge pump circuit. In addition, the charge pump voltage regulator includes a first voltage comparator circuit suitable to output at least one of a first comparison result and a second comparison result. Further, the charge pump voltage regulator includes a logic control unit, where, when the charge pump voltage regulator operates in a standby mode, the logic control unit outputs a first control level to the clock oscillator according to the at least one of the first comparison result and the second comparison result.

Abstract: A memory and a reference circuit calibration method are provided. The memory includes: a memory array including a plurality of memory cells; a reference circuit including a reference memory cell and a reference connection terminal, wherein the reference memory cell is a same as the memory cell; a calibration circuit including a calibration connection terminal, and a mirror circuit including a first mirror terminal and a second mirror terminal, wherein the first mirror terminal is connected to the reference connection terminal, and the second mirror terminal is connected to the calibration connection terminal; a clamp circuit, configured to set one of a voltage of the reference connection terminal and a voltage of the calibration connection terminal as a preset voltage and to set the other thereof as a comparison voltage; and a comparison circuit configured to input the comparison voltage and the preset voltage, and to output a comparison result.

Abstract: Memory arrays and reading, programming and erasing methods of the memory arrays are provided. An exemplary memory array includes a plurality of memory columns. Each memory column has a plurality of flash memory cells. The memory columns are divided into at least two blocks. At least one source pull down column is disposed between the two adjacent blocks. Each source pull down column has a plurality of flash memory cells. A source of each flash memory cell in the source pull down column is coupled to sources of the flash memory cells of the plurality memory columns in a same row as the flash memory cell in the source pull down column to pull down a source of a selected flash memory cell to 0 V.

Abstract: A virtual reality goggle includes a goggle shaped body having multiple cameras mounted thereon. A display is supported by the goggle shaped body. A support extends between sides of the goggle shaped body and includes multiple cameras. Circuitry is coupled to receive video from the multiple cameras, the video comprising a composite field of view of approximately 360 degrees about the goggle, the circuitry to couple to a wireless communication device to transmit the received video to networked processing services, and to receive stitched stereoscopic three dimensional virtual reality video from the networked processing services, the circuitry further coupled to provide the received stitched stereoscopic three dimensional virtual reality video for display.

Abstract: A virtual reality goggle includes a goggle shaped body having multiple cameras mounted thereon. A display is supported by the goggle shaped body. A support extends between sides of the goggle shaped body and includes multiple cameras. Circuitry is coupled to receive video from the multiple cameras, the video comprising a composite field of view of approximately 360 degrees about the goggle, the circuitry to couple to a wireless communication device to transmit the received video to networked processing services, and to receive stitched stereoscopic three dimensional virtual reality video from the networked processing services, the circuitry further coupled to provide the received stitched stereoscopic three dimensional virtual reality video for display.

Abstract: A memory and a reference circuit calibration method are provided. The memory includes: a memory array including a plurality of memory cells; a reference circuit including a reference memory cell and a reference connection terminal, wherein the reference memory cell is a same as the memory cell; a calibration circuit including a calibration connection terminal and a mirror circuit including a first mirror terminal and a second mirror terminal, wherein the first mirror terminal is connected to the reference connection terminal, and the second mirror terminal is connected to the calibration connection terminal; a clamp circuit, configured to set one of a voltage of the reference connection terminal and a voltage of the calibration connection terminal as a preset voltage and to set the other thereof as a comparison voltage; and a comparison circuit configured to input the comparison voltage and the preset voltage, and to output a comparison result.

Abstract: A virtual reality goggle includes a goggle shaped body having multiple cameras mounted thereon. A display is supported by the goggle shaped body. A support extends between sides of the goggle shaped body and includes multiple cameras. Circuitry is coupled to receive video from the multiple cameras, the video comprising a composite field of view of approximately 360 degrees about the goggle, the circuitry to couple to a wireless communication device to transmit the received video to networked processing services, and to receive stitched stereoscopic three dimensional virtual reality video from the networked processing services, the circuitry further coupled to provide the received stitched stereoscopic three dimensional virtual reality video for display.

Abstract: A charge pump voltage regulator is provided. The charge pump voltage regulator includes a charge pump circuit, where an output terminal of the charge pump circuit outputs a stable voltage. The charge pump voltage regulator also includes a voltage divider circuit suitable to divide the stable voltage to output a divided voltage and a clock oscillator providing a drive clock signal for the charge pump circuit. In addition, the charge pump voltage regulator includes a first voltage comparator circuit suitable to output at least one of a first comparison result and a second comparison result. Further, the charge pump voltage regulator includes a logic control unit, where, when the charge pump voltage regulator operates in a standby mode, the logic control unit outputs a first control level to the clock oscillator according to the at least one of the first comparison result and the second comparison result.

Abstract: Concepts herein relate to processing urine sediment images. An example method comprises: approximating the color of a pixel in a block to be processed to one of the kc colors in a code book, wherein the code book is a set of the kc colors generated in a set of urine sample blocks; obtaining a distribution histogram of the number of pixels the color approximation results of which fall on each color of the kc colors; using an occurrence frequency correction factor to correct the number of pixels the color approximation results; standardizing the corrected number of pixels the color approximation results; and processing the block to be processed.

Abstract: An apparatus for enqueuing kernels on a device-side is introduced to incorporate with at least a MXU (Memory Access Unit) and a CSP (Command Stream Processor): The CSP, after receiving a first command from the MXU, executes commands of a ring buffer, thereby enabling an EU (Execution Unit) to direct the MXU to allocate space of the ring buffer for a first hardware thread and subsequently write second commands of the first hardware thread into the allocated space of the ring buffer according to an instruction of a kernel.

Abstract: A method for generating machine code for driving an execution unit is introduced to incorporate with at least the following steps: Data access instructions of a kernel, which are associated with the same memory surface, are collected. An address pattern associated with the data access instructions is analyzed to generate a global-id address. Machine code containing the global-id address is generated.

Abstract: A method for computing trigonometric functions, performed by an ALU (Arithmetic Logic Unit) in coordination with an SFU (Special Function Unit), is introduced to contain at least the following steps. The ALU computes a remainder r and a reduction value x* corresponding to an input parameter x. The SFU computes an intermediate function f(x*) corresponding to the reduction value x*. The ALU computes a multiplication of the reduction value x* by the intermediate function f(x*) as the computation result of a trigonometric function.

Abstract: Concepts herein relate to processing urine sediment images. An example method comprises: approximating the color of a pixel in a block to be processed to one of the kc colors in a code book, wherein the code book is a set of the kc colors generated in a set of urine sample blocks; obtaining a distribution histogram of the number of pixels the color approximation results of which fall on each color of the kc colors; using an occurrence frequency correction factor to correct the number of pixels the color approximation results; standardizing the corrected number of pixels the color approximation results; and processing the block to be processed.

Abstract: The inventive concepts herein relate to performing block retrieval on a block to be processed of a urine sediment image. The method comprises: using a plurality of decision trees to perform block retrieval on the block to be processed, wherein each of the plurality of decision trees comprises a judgment node and a leaf node, and the judgment node judges the block to be processed to make it reach the leaf node by using a block retrieval feature in a block retrieval feature set to form a block retrieval result at the leaf node, and at least two decision trees in the plurality of decision trees are different in structures thereof and/or judgments performed by the judgment nodes thereof by using the block retrieval feature; and integrating the block retrieval results of the plurality of decision trees so as to form a final block retrieval result.

Abstract: A handheld device for canceling unintentional muscle movement. The device includes a base comprising a handgrip for a user to hold, a gripping element linked to the base for releasably connecting the handheld device to an object, a sensor that detects movement of the base, a controller linked to the sensor, and at least one actuator that operates under control of the controller to cause movement of the gripping element in a direction that at least partially counteracts the detected movement of the base.

Abstract: A handheld device for canceling unintentional muscle movement. The device includes a base comprising a handgrip for a user to hold, a gripping element linked to the base for releasably connecting the handheld device to an object, a sensor that detects movement of the base, a controller linked to the sensor, and at least one actuator that operates under control of the controller to cause movement of the gripping element in a direction that at least partially counteracts the detected movement of the base.

Abstract: An apparatus comprises a matrix of thermoelectric devices for applying thermal gradients across an electronic component mounted in a PCB substrate within an enclosed housing. A matrix of thermosensitive devices are placed around the perimeter of the electronic component to measure thermal gradients associated with the component. A controller controls the matrix of thermoelectric devices based on the thermal gradients measured by the matrix of thermosensitive devices with a matrix of thermocouple coefficients.

Abstract: An apparatus and method are described for synchronizing distribution of packet information. In one embodiment, the invention includes timestamp processing logic to process a transmit time indicator embedded within the packet information, where the transmit time indicator is based on a time reference, and service synchronization queuing logic to hold the packet information until a time offset after the transmit time indicator, where the service synchronization queuing logic is synchronized to the time reference.

Abstract: An apparatus comprises a matrix of thermoelectric devices for applying thermal gradients across an electronic component mounted in a PCB substrate within an enclosed housing. A matrix of thermosensitive devices are placed around the perimeter of the electronic component to measure thermal gradients associated with the component. A controller controls the matrix of thermoelectric devices based on the thermal gradients measured by the matrix of thermosensitive devices with a matrix of thermocouple coefficients.

Abstract: An apparatus comprises a matrix of thermoelectric devices for applying thermal gradients across an electronic component mounted in a PCB substrate within an enclosed housing. A matrix of thermosensitive devices are placed around the perimeter of the electronic component to measure thermal gradients associated with the component. A controller controls the matrix of thermoelectric devices based on the thermal gradients measured by the matrix of thermosensitive devices with a matrix of thermocouple coefficients.