Abstract: The present invention is related to a self-aligned manufacturing method of a thin film transistor for forming a single-crystal bottom-gate and an offset drain. The main object of the present invention is to disclose two manufacturing methods to attain the self-aligned manufacturing method of a thin film transistor for forming a single-crystal bottom-gate and an offset drain. In the first method, a photoresistor and a silicon nitride are used to form a dual stack as a mask, further a large-angle ion implant is used to form a thin film transistor with a single-crystal bottom-gate and an offset drain. In the second method, the source side is protected by a dual stack formed by a P+ polysilicon layer which may be discarded selectively and a silicon nitride and an insulation spacer of sidewall in order to selectively discard the silicon nitride on the drain side, thus the object of a thin film transistor with a single-crystal bottom-gate and an offset drain is obtained.

Abstract: A method for formation of both local innerconnection and silicidation of source/drain transistors using the deposition of a blanket silicon layer over the entire top surface of the transistors and selectively stripping of unwanted portions of the silicon layer is disclosed. The method includes the step of applying a photoresist mask to map out where the local interconnection and source/drain are to be located. The final recited step is to deposit a thin metal layer to provide for the silicidation to complete the transistor. The silicon layer that is deposited has a thickness of 20 to 300 millimeters, and the thin metal layer is either cobalt or titanium having a thickness of 10 millimeters to 100 millimeters.

Abstract: A new method for manufacturing an MOS transistor is applied in the deep submicron process. In this method, a polysilicon layer is mainly used to form a raised source/drain structure and self-alignment is achieved by means of a planarization process. This method can reduce short channel effects and the series impedance of the source/drain as well as accomplish the local interconnection of a circuit and planarization. Therefore, this method is very suitable for manufacturing devices in the deep submicron process.

Abstract: A MOS transistor is fabricated by forming an inverse gate mask consisting of a lower silicon dioxide layer and an upper silicon nitride layer. The exposed channel region is thermally oxidized. The mask is removed to permit a source/drain implant. The oxide growth is removed so that the channel region is recessed. A differential oxide growth then serves to mask the source and the drain for channel threshold adjust and punch-through implants. A doped polysilicon gate is formed, with the thinner area of the differential oxide serving as the gate oxide. In the resulting structure, the punch-through dopant is spaced from the source and the drain, reducing parasitic capacitance and improving transistor switching speeds.

Abstract: A structure and method for manufacturing improved FETs having T-shaped gates can reduce the parasitic resistance of the gate and source/drain of an FET. In the improved FETs having T-shaped gates formed according to the invention, since a buffer layer under spacers comprises a gate oxide layer and a thicker first dielectric layer, there is no stress problem as in the prior art. Furthermore, since the polysilicon gate is lower in height than the spacers, a bridge effect can be prevented. Meanwhile, since a T-shaped conductive layer is formed to increase the equivalent width of the gate, thereby avoiding the narrow line-width effect.

Abstract: An input buffer for a CMOS integrated circuit comprises parallel pairs of complementary PMOS pull-up and NMOS pull-down transistors. For each NMOS transistor, a polysilicon NMOS gate lead structure includes three sections: a heavily doped gate section, an undoped resistor section, and a heavily doped contact section. The heavily doped contact section is contacted by a metal delivering a logic low voltage (V.sub.SS) so that the NMOS gate is resistively coupled to V.sub.SS. This resistance cooperates with the gate to drain resistance to define a voltage divider between V.sub.SS and V.sub.IN. This voltage divider leaves the gate at a small positive voltage during an electrostatic discharge event. This ensures that all NMOS transistors of a buffer become current bearing before any of them enters second breakdown. This arrangement maximizes input-buffer protection from electrostatic discharge events. The novel NMOS arrangement is readily compatible with CMOS fabrication techniques.

Abstract: The present invention provides a CMOS integrated circuit in which core transistors are provided with punch-through pockets, while the input/output transistors are not provided with punch-through pockets. Punch-through protection for the input/output transistors by virtue of their larger dimensions. The pockets, like lightly doped drains, are formed after the gates are formed but before the formation of gate sidewalls. However, the input/output are masked during the punch-through implants, but are unmasked for at least one of the lightly doped drain implants. The absence of pockets on the input/output transistors enhances their ESD resistance, and thus the ESD resistance of the incorporating integrated circuit.

Abstract: An input buffer for a CMOS integrated circuit comprises parallel pairs of complementary PMOS pull-up and NMOS pull-down transistors. For each NMOS transistor, a polysilicon NMOS gate lead structure includes three sections: a heavily doped gate section, an undoped resistor section, and a heavily doped contact section. The heavily doped contact section is contacted by a metal delivering a logic low voltage (V.sub.SS) so that the NMOS gate is resistively coupled to V.sub.SS. This resistance cooperates with the gate to drain resistance to define a voltage divider between V.sub.SS and V.sub.IN. This voltage divider leaves the gate at a small positive voltage during an electrostatic discharge event. This ensures that all NMOS transistors of a buffer become current bearing before any of them enters second breakdown. This arrangement maximizes input-buffer protection from electrostatic discharge events. The novel NMOS arrangement is readily compatible with CMOS fabrication techniques.

Abstract: A method for making an integrated circuit in accordance with the present invention comprises fabricating at least one functional MOSFET with a hot electron resistant structure including a lightly doped drain, fabricating at least one output MOSFET with an ESD resistant structure including a gate means without associated spacers, and electrically coupling at least one functional MOSFET to at least one output MOSFET. An integrated circuit structure in accordance with the present invention includes at least one functional MOSFET having a hot electron resistant structure including a LDD drain, at least one output MOSFET having an ESD resistant structure including a gate means without associated spacers, and means for electrically coupling the two together. The functional MOSFET includes a gate insulator, a conductive gate region over the gate insulator, spacers along the sidewalls of the gate insulator and conductive gate regions, a pair of LDD regions, and source/drain regions.

Abstract: The present invention provides a CMOS integrated circuit in which core transistors are provided with punch-through pockets, while the input/output transistors are not provided with punch-through pockets. Punch-through protection for the input/output transistors by virtue of their larger dimensions. The pockets, like lightly doped drains, are formed after the gates are formed but before the formation of gate sidewalls. However, the input/output are masked during the punch-through implants, but are unmasked for at least one of the lightly doped drain implants. The absence of pockets on the input/output transistors enhances their ESD resistance, and thus the ESD resistance of the incorporating integrated circuit.

Abstract: An input buffer for a CMOS integrated circuit comprises parallel pairs of complementary PMOS pull-up and NMOS pull-down transistors. Floating NMOS gates are capacitively coupled to V.sub.SS by a first-level metalization pattern. The metal-to-gate overlap capacitance and the gate-to-drain overlap capacitance define a voltage divider that leaves the gate at a small positive voltage during an electrostatic discharge event. This ensures that all NMOS transistors of a buffer enter a conducting bipolar mode before any of them enters second breakdown. This arrangement maximizes input-buffer protection from electrostatic discharge events. The novel NMOS arrangement is readily compatible with gate array designs.

Abstract: A silicon-on-insulator transistor structure includes a selectively thinned channel region, leaving the source and drain regions relatively thick. The relatively thin channel region provides for full depletion, larger current handling, and thus, faster operation. The relatively thick source and drain regions provide resistance to damage by electrostatic discharge. The transistor structure can be formed from a silicon-on-insulator wafer by performing a light, deep source/drain implant; a shallow, heavy source/drain implant is optionally performed at this stage. Source and drain regions are masked, while the channel regions are etched to the desired channel thickness. After the mask material is removed, a gate oxide can be grown; gates can then be defined. If it has not been performed earlier, the shallow heavy source/drain implant can be performed at this point. In addition, a channel threshold adjust implant can be performed after the channel regions are thinned and before the gates are formed.

Abstract: Selective salicidation of source/drain regions of a transistor is accomplished by differentially treating a first subset of the source/drain regions to hinder formation of metal-silicide over the first subset of the source/drain regions. A metal layer is formed over the first subset of the source/drain regions and a second subset of the source/drain regions. The metal layer is annealed at a temperature such that the metal reacts to form metal-silicide over the second subset of the source/drain regions, but not over the first subset of the source/drain regions. The unreacted metal is stripped off over the first subset of the source/drain regions. In the preferred embodiment of the present invention, a second anneal is then performed to fully form metal-silicide over the second subset of the source/drain regions.

Abstract: A CMOS SRAM cell includes "true" and "false" NMOS word-line access transistors, "true" and "false" NMOS pull-down transistors, and "true" and "false" PMOS pull-down transistors arranged in a classical six-transistor SRAM electrical configuration. "True" and "false" inter-level interconnects of silicidable material provide for respective five-way connections among the transistors. The "true" inter-level interconnect connects: the drain of the "true" pull-up transistor, a gate level polysilicon conductor defining and connecting the gates of the "false" pull-up transistor and the "false" pull-down transistor, and a diffusion region defining and connecting the source of the "true" access transistor and the drain of the "true" pull-down transistor.

Abstract: An asymmetric electro-static discharge transistor includes a gate region formed on a substrate. The gate region includes a polysilicon gate region placed over a dielectric layer. A drain region is placed within the substrate. The drain region includes a first drain region implanted with atoms of a first conductivity type at a first concentration. The first drain region extends under the gate region. For example, the first drain region is a lightly doped n.sup.- region. A second drain region is formed adjacent to the first doped portion. The second drain region is implanted with atoms of the first conductivity type. For example, the second drain region is a heavily doped n.sup.+ region. A source region is formed within the substrate. The source region extends under the gate region. The source region is implanted with atoms of the first conductivity type. For example, the source region is a heavily doped n.sup.+ region.

Abstract: Selective salicidation of source/drain regions of a transistor is accomplished by performing an implant into a first plurality of transistor source/drain regions on an integrated circuit. As a result of the implant, doping density of the first plurality of transistor source/drain regions is greater than doping density of a second plurality of transistor source/drain regions on the integrated circuit. The integrated circuit is heated to a heating temperature sufficient to produce oxidation regions immediately over the first plurality of transistor source/drain regions and the second plurality of transistor source/drain regions. The heating temperature is chosen so that the oxidation regions immediately over the first plurality of transistor source/drain regions are thicker than the oxidation regions immediately over the second plurality of transistor source/drain regions.

Abstract: This disclosure relates to semiconductor varactors, such as thin film poly-Si varactors, which have larger effective gate areas in accumulation than in depletion, together with capacitive switching ratios which are essentially determined by the ratio of their effective gate area in accumulation to their effective gate area in depletion. To that end, such a varactor has a fully depletable active semiconductor layer, such as a thin poly-Si film, and is constructed so that at least a part of its active layer is sandwiched between a relatively thin dielectric layer and a relatively thick dielectric layer. The thin dielectric layer, in turn, is sandwiched between the active semiconductor layer and a gate electrode. Furthermore, one or more ground electrodes are electrically coupled to laterally offset portions of the active semiconductor layer in partial overlapping alignment with the gate electrode.

Abstract: A thin film SOI CMOS device wherein the suitably doped deposited layers of an n-channel transistor and a p-channel transistor are simultaneously deposited. The source and drain elements of one transistor and the gate element of the other transistor are formed in a lower, highly doped, semiconductor layer and are separated from the corresponding gate element and source and drain elements formed in an upper, highly doped, semiconductor layer. The layer levels are separated by two intrinsic or lightly doped semiconductor layers sandwiching a dielectric layer, so that the intrinsic or lightly doped semiconductor layer lying contiguous to the source and drain elements serves as an active channel layer and the intrinsic or lightly doped semiconductor layer lying contiguous to the gate element serves to extend the gate layer.

Abstract: An improved double implanted and aligned LDD transistor comprising a gate having a central alignment member and a pair of outboard alignment members having portions contiguous with the gate oxide layer. A lightly doped junction is aligned with the central alignment member and a heavily doped junction is aligned with the outboard alignment members.

Abstract: A thin film SOI CMOS device wheren the suitably doped deposited layers of an n-channel transistor and a p-channel transistor are simultaneously deposited. The source and drain elements of one transistor and the gate element of the other transistor are formed in a lower, highly doped, semiconductor layer and are separated from the corresponding gate element and source and drain elements formed in an upper, highly doped, semiconductor layer. The layer levels are separated by two intrinsic or lightly doped semiconductor layers sandwiching a dielectric layer, so that the intrinsic or lightly doped semiconductor layer lying contiguous to the source and drain elements serves as an active channel layer and the intrinsic or lightly doped semiconductor layer lying contiguous to the gate element serves to extend the gate layer.